Texas Instruments LDC3114 Manual Download Page 13

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Ack

Slave

Start by

Master

R/W

Ack

Slave

Frame 1

Serial Bus Address Byte

from Master

Frame 2

Slave Register Address (ADDR) from

Master

Ack

Slave

Frame 3

Data Byte to

SCL

SDA

SCL
(continued)

SDA
(continued)

Ack

Slave

Frame N+3

Data Byte to Register

ADDR+N

SCL
(continued)

SDA
(continued)

Stop by

Master

Frame 4

Data Byte to

Ack

Slave

Figure 7-5. I

C Sequence of Writing Consecutive Registers

Ack

Slave

Start by

Master

R/W

Ack

Slave

Frame 1

Serial Bus Address Byte

from Master

Frame 2

Slave Register Address from Master

SCL

SDA

SCL
(continued)

SDA
(continued)

Ack

Slave

Repeat

Start by

Master

No Ack

Master

Stop

Master

Frame 3

Serial Bus Address Byte

from Master

R/W

Frame 4

Data Byte from Slave

Figure 7-6. I

C Sequence of Reading a Single Register

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LDC3114

SNOSDD0 – DECEMBER 2021

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LDC3114

Summary of Contents for LDC3114

Page 1: ...rinted circuit board PCB located behind the panel This technology can be used for precise linear position sensing of metal targets for automotive consumer and industrial applications by allowing access to the raw data representing the inductance value Inductive sensing solution is insensitive to humidity or non conductive contaminants such as oil and dirt The button mode of LDC3114 is able to auto...

Page 2: ...s 14 7 5 Register Maps 15 8 Application and Implementation 37 8 1 Application Information 37 8 2 Typical Application 48 9 Power Supply Recommendations 51 10 Layout 51 10 1 Layout Guidelines 51 10 2 Layout Example 51 11 Device and Documentation Support 52 11 1 Documentation Support 52 11 2 Receiving Notification of Documentation Updates 52 11 3 Support Resources 52 11 4 Trademarks 52 11 5 Electrost...

Page 3: ...Refer to Setting COM Pin Capacitor IN0 9 A Channel 0 LC sensor input IN1 8 A Channel 1 LC sensor input IN2 7 A Channel 2 LC sensor input IN3 6 A Channel 3 LC sensor input OUT0 15 O Channel 0 logic output Polarity can be configured in Register 0x1C OUT1 13 O Channel 1 logic output Polarity can be configured in Register 0x1C OUT2 12 O Channel 2 logic output Polarity can be configured in Register 0x1...

Page 4: ...ing with a standard ESD control process 2 JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process 6 3 Recommended Operating Conditions Over operating temperature range unless otherwise noted MIN NOM MAX UNIT VDD Supply voltage 1 71 1 89 V TA Ambient temperature TSSOP Package 40 125 C 6 4 Thermal Information THERMAL METRIC 1 LDC3114 UNIT TSSOP 16 PI...

Page 5: ...ce to COM 0 9 V CIN Sensor input pin capacitance 17 pF CONVERTER SRNP MIN Minimum normal power mode scan rate 5 LPWRB VDD 7 10 13 SPS SRNP MAX Maximum normal power mode scan rate 5 LPWRB VDD 56 80 104 SPS SRLP MIN Minimum low power mode scan rate 5 LPWRB Ground 0 438 0 625 0 813 SPS SRLP MAX Maximum low power mode scan rate 5 LPWRB Ground 3 5 5 6 5 SPS fREF_CLK Internal Reference clock frequency T...

Page 6: ...tHD STA Hold time repeated START condition After this period the first clock pulse is generated 0 6 µs tSU STA Set up time for a repeated START condition 0 6 µs tHD DAT Data hold time 0 µs tSU DAT Data set up time 100 ns tSU STO Set up time for STOP condition 0 6 µs tBUF Bus free time between a STOP and START condition 1 3 µs tVD DAT Data valid time 0 9 µs tVD ACK Data valid acknowledge time 0 9 µ...

Page 7: ... Sensor RP for Normal Power Mode Sensor Frequency 10 MHz Sampling Window 2mS Two Channels Enabled Figure 6 4 Supply Current vs Sensor RP for Low Power Mode Sensor Frequency 10 MHz Figure 6 5 Supply Current vs Temperature Sensor RP 720 Ω Scan Rate 40 SPS Sensor Frequency 20 MHz Figure 6 6 Supply Current vs VDD Sensor RP 720 Ω Scan Rate 40 SPS Sensor Frequency 20 MHz Figure 6 7 Standby Current vs Te...

Page 8: ...ndow of 1 ms unless specified otherwise Figure 6 8 Standby Current vs VDD Percentage Offset Occurrences 0 50 100 150 200 250 300 350 400 450 12 11 10 9 8 7 6 5 4 3 2 1 0 1 2 3 4 D007 Figure 6 9 Scan Rate Distribution at 30 C LDC3114 SNOSDD0 DECEMBER 2021 www ti com 8 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated Product Folder Links LDC3114 ...

Page 9: ...lay or other low latency applications The LDC3114 is operational from 40 C to 125 C with a 1 8 V 5 power supply voltage The LDC3114 is configured through 400 kHz I2C Button presses can be reported through the I2C interface or with configurable polarity dedicated push pull outputs Besides the LC resonant sensors the only external components necessary for operation are supply bypassing capacitors an...

Page 10: ...active the LDC3114 periodically samples the single active channel at the configured scan rate When several channels are set active the LDC3114 operates in multichannel mode and the device sequentially samples the active channels at the configured scan rate Each channel of the LDC3114 can be independently enabled in Low Power Mode and Normal Power Mode 7 3 3 Raw Data Output Raw data mode is enabled...

Page 11: ...C3114 incorporates a baseline tracking algorithm to automatically compensate for any slow change in the sensor output caused by environmental variations such as temperature drift The baseline tracking is configured independently for Normal Power Mode and Low Power Mode For more information refer to Tracking Baseline Note The baseline tracking feature is applicable only for button algorithm functio...

Page 12: ...el translation between LDC3114 and the MCU 7 3 8 1 I2C Interface Specifications The maximum speed of the I2C interface is 400 kHz This sequence uses the standard I2C 7 bit target address followed by an 8 bit pointer to set the register address For both write and read the address pointer will auto increment as long as the controller acknowledges D7 D6 D5 D4 D3 D2 D1 D0 1 9 1 9 Ack by Slave Start by...

Page 13: ... 1 Ack by Slave Figure 7 5 I2C Sequence of Writing Consecutive Registers D7 D6 D5 D4 D3 D2 D1 D0 1 9 1 9 Ack by Slave Start by Master R W Ack by Slave Frame 1 Serial Bus Address Byte from Master Frame 2 Slave Register Address from Master A2 A0 A1 A3 A4 A5 A6 SCL SDA SCL continued SDA continued D7 D6 D5 D4 D3 D2 D1 D0 1 9 Ack by Slave Repeat Start by Master No Ack by Master Stop by Master 1 9 Frame...

Page 14: ...er should send nine clock pulses The device that is holding the bus LOW should release the bus sometime within those nine clocks If not then power cycle to clear the bus The LDC3114 has built in monitors to check that the device is currently working In the unlikely event of a device fault the device state will be reset internally and all the registers will be reset with default settings For system...

Page 15: ...NFIG_MODE 0 for normal operation Refer to I2C Interface for more information 7 5 Register Maps 7 5 1 LDC3114 Registers LDC3114 Registers lists the memory mapped registers for the LDC3114 registers All register offset addresses not listed in LDC3114 Registers should be considered as reserved locations and the register contents should not be modified Table 7 1 LDC3114 Registers Offset Acronym Regist...

Page 16: ...SOR3_CONFIG Sensor3 cycle count frequency RP range Section 7 5 1 33 28h FTF1_2 Sensors 1 and 2 fast tracking factors for button algorithm Section 7 5 1 34 2Bh FTF3 Sensor 3 fast tracking factor for button algorithm Section 7 5 1 35 59h RAW_DATA0_3 Sensor 0 pre processed raw data Section 7 5 1 36 5Ah RAW_DATA0_2 Sensor 0 pre processed raw data Section 7 5 1 37 5Bh RAW_DATA0_1 Sensor 0 pre processed...

Page 17: ...Maximum Output Code Indicates if any channel button output data reaches the maximum value 0x7FF or 0x800 Cleared by a read of the status register 0h No maximum output code 1h Maximum output code 3 FSM_WD R 0h Finite State Machine Watchdog Error Reports an error has occurred and conversions have been halted Cleared by a read of the status register 0h No error in finite state machine 1h Error in fin...

Page 18: ...output Logic State for Channel 2 0h No button press detected on Channel 2 1h Button press detected on Channel 2 1 OUT1 R 0h Button output Logic State for Channel 1 0h No button press detected on Channel 1 1h Button press detected on Channel 1 0 OUT0 R 0h Button output Logic State for Channel 0 0h No button press detected on Channel 0 1h Button press detected on Channel 0 7 5 1 3 DATA0_LSB Register...

Page 19: ...set Description 7 4 RESERVED R 0h Reserved 3 0 DATA1 11 8 R 0h The upper 4 bits of Channel 1 button data Two s complement 7 5 1 7 DATA2_LSB Register Offset 6h Reset 00h DATA2_LSB is shown in DATA2_LSB Register Field Descriptions Return to the LDC3114 Registers The lower 8 bits of the Button 2 data Two s complement Table 7 9 DATA2_LSB Register Field Descriptions Bit Field Type Reset Description 7 0...

Page 20: ...n to the LDC3114 Registers Reset device and register configurations Table 7 13 RESET Register Field Descriptions Bit Field Type Reset Description 7 5 RESERVED R W 0h Reserved 4 FULL_RESET R W 0h Device Reset 0h Normal operation 1h Resets the device and register configurations All registers will be returned to default values Normal operation will not resume until STATUS CHIP_READY 1 3 1 RESERVED R ...

Page 21: ...nnel 2 1 EN1 R W 1h Channel 1 Enable 0h Disable Channel 1 1h Enable Channel 1 0 EN0 R W 1h Channel 0 Enable 0h Disable Channel 0 1h Enable Channel 0 7 5 1 13 NP_SCAN_RATE Register Offset Dh Reset 01h NP_SCAN_RATE is shown in NP_SCAN_RATE Register Field Descriptions Return to the LDC3114 Registers Normal Power Mode scan rate Table 7 15 NP_SCAN_RATE Register Field Descriptions Bit Field Type Reset D...

Page 22: ...own in LP_SCAN_RATE Register Field Descriptions Return to the LDC3114 Registers Low Power Mode scan rate Table 7 17 LP_SCAN_RATE Register Field Descriptions Bit Field Type Reset Description 7 2 RESERVED R W 4h Reserved 1 0 LPSR R W 0h Low Power Mode Scan Rate Refer to Configuring Button Scan Rate section for more information 0h 5 SPS 1h 2 5 SPS 2h 1 25 SPS Default 3h 0 625 SPS 7 5 1 16 GAIN1 Regis...

Page 23: ...r for error events When disabled events on OUT_x pins pins are ignored to assert interrupt on INTB pin 0h Disable Button Algorithm 1h Enable Button Algorithm 2 INTPOL R W 0h Interrupt Polarity 0h Set INTB pin polarity to active low 1h Set INTB pin polarity to active high 1 DIS_BTN_TO R W 0h Disable Button time out if if button pressed for more than 50s 0h Enable Button Timeout 1h Disable Button Ti...

Page 24: ...ent for button algorithm Table 7 23 NP_BASE_INC Register Field Descriptions Bit Field Type Reset Description 7 3 RESERVED R W 0h Reserved 2 0 NPBI R W 3h Baseline Tracking Increment in Normal Power Mode for button algorithm Refer to Tracking Baseline section for more information 7 5 1 22 BTPAUSE_MAXWIN Register Offset 16h Reset 00h BTPAUSE_MAXWIN is shown in BTPAUSE_MAXWIN Register Field Descripti...

Page 25: ...ing for Channel 3 Refer to Resolving Simultaneous Button Presses Max Win section for more information 0h Exclude Channel 3 from the max win group 1h Include Channel 3 in the max win group 2 MAXWIN2 R W 0h Max Win Button Algorithm Setting for Channel 2 Refer to Resolving Simultaneous Button Presses Max Win section for more information 0h Exclude Channel 2 from the max win group 1h Include Channel 2...

Page 26: ...eset Description 7 3 RESERVED R W 0h Reserved 2 0 ANTITWIST R W 0h Anti Twist When set to 0 the anti twist for button algorithm is not enabled When greater than 0 all buttons are enabled for the anti twist button algorithm The validation of all buttons is void if any button s BTN_DATA is negative by a threshold Anti twist Threshold ANTITWIST 4 Refer to Overcoming Case Twisting Anti Twist section f...

Page 27: ...el 2 Refer to Mitigating Metal Deformation Anti Deform section for more information 0h Exclude Channel 2 from the anti deform group 1h Include Channel 2 in the anti deform group 1 ANTIDFORM1 R W 0h Anti Deform Button Algorithm Setting for Channel 1 Refer to Mitigating Metal Deformation Anti Deform section for more information 0h Exclude Channel 1 from the anti deform group 1h Include Channel 1 in ...

Page 28: ...OR0 increases 1h DATA0 increases as fSENSOR0 increases 7 5 1 28 CNTSC Register Offset 1Eh Reset 55h CNTSC is shown in CNTSC Register Field Descriptions Return to the LDC3114 Registers Counter scale Table 7 30 CNTSC Register Field Descriptions Bit Field Type Reset Description 7 6 CNTSC3 R W 1h Counter Scale for Channel 3 Refer to Scaling Frequency Counter Output section for more information 0h CNTS...

Page 29: ...o 3 3 MHz 1h 3 3 MHz to 10 MHz 2h 10 MHz to 30 MHz 3h Reserved 4 0 SENCYC0 R W 4h Channel 0 Sensor Cycle Count SENCYC0 sets the Channel 0 button sampling window in conjunction with LCDIV Refer to Programming Button Sampling Window section for more information 7 5 1 30 SENSOR1_CONFIG Register Offset 22h Reset 04h SENSOR1_CONFIG is shown in SENSOR1_CONFIG Register Field Descriptions Return to the LD...

Page 30: ...ormation 0h 1 MHz to 3 3 MHz 1h 3 3 MHz to 10 MHz 2h 10 MHz to 30 MHz 3h Reserved 4 0 SENCYC2 R W 4h Channel 2 Sensor Cycle Count SENCYC2 sets the Channel 2 button sampling window in conjunction with LCDIV Refer to Programming Button Sampling Window section for more information 7 5 1 32 FTF0 Register Offset 25h Reset DAh FTF0 is shown in FTF0 Register Field Descriptions Return to the LDC3114 Regis...

Page 31: ... Register Field Descriptions Return to the LDC3114 Registers Sensors 1 and 2 fast tracking factors for button algorithm Table 7 36 FTF1_2 Register Field Descriptions Bit Field Type Reset Description 7 6 FTF2 R W 1h Fast Tracking Factor for Channel 2 Defines baseline tracking for button algorithm speed for negative values of DATA2 Refer to Tracking Baseline section for more information 0h FTF2 is 0...

Page 32: ...00h RAW_DATA0_2 is shown in RAW_DATA0_2 Register Field Descriptions Return to the LDC3114 Registers Sensor 0 pre processed raw data Table 7 39 RAW_DATA0_2 Register Field Descriptions Bit Field Type Reset Description 7 0 RAW_DATA0 15 8 R 0h Sensor 0 pre processed raw data 7 5 1 38 RAW_DATA0_1 Register Offset 5Bh Reset 00h RAW_DATA0_1 is shown in RAW_DATA0_1 Register Field Descriptions Return to the...

Page 33: ... 1 pre processed raw data 7 5 1 42 RAW_DATA2_3 Register Offset 5Fh Reset 00h RAW_DATA2_3 is shown in RAW_DATA2_3 Register Field Descriptions Return to the LDC3114 Registers Sensor 2 pre processed raw data Table 7 44 RAW_DATA2_3 Register Field Descriptions Bit Field Type Reset Description 7 0 RAW_DATA2 7 0 R 0h Sensor 2 pre processed raw data 7 5 1 43 RAW_DATA2_2 Register Offset 60h Reset 00h RAW_D...

Page 34: ...h Sensor 3 pre processed raw data 7 5 1 47 RAW_DATA3_1 Register Offset 64h Reset 00h RAW_DATA3_1 is shown in RAW_DATA3_1 Register Field Descriptions Return to the LDC3114 Registers Sensor 3 pre processed raw data Table 7 49 RAW_DATA3_1 Register Field Descriptions Bit Field Type Reset Description 7 0 RAW_DATA3 23 16 R 0h Sensor 3 pre processed raw data 7 5 1 48 MANUFACTURER_ID_LSB Register Offset F...

Page 35: ... byte Table 7 52 DEVICE_ID_LSB Register Field Descriptions Bit Field Type Reset Description 7 0 DEVICE_ID_ 7 0 R 0h Device ID 7 0 7 5 1 51 DEVICE_ID_MSB Register Offset FFh Reset 40h DEVICE_ID_MSB is shown in DEVICE_ID_MSB Register Field Descriptions Return to the LDC3114 Registers Device ID upper byte Table 7 53 DEVICE_ID_MSB Register Field Descriptions Bit Field Type Reset Description 7 0 DEVICE...

Page 36: ...1 6875 38 27 7 1 8125 39 29 8 2 0 40 32 9 2 125 41 34 10 2 375 42 38 11 2 625 43 42 12 2 875 44 46 13 3 125 45 50 14 3 375 46 54 15 3 625 47 58 16 4 0 48 64 17 4 25 49 68 18 4 75 50 76 19 5 25 51 84 20 5 75 52 92 21 6 25 53 100 22 6 75 54 108 23 7 25 55 116 24 8 0 56 128 25 8 5 57 136 26 9 5 58 152 27 10 5 59 168 28 11 5 60 184 29 12 5 61 200 30 13 5 62 216 31 14 5 63 232 LDC3114 SNOSDD0 DECEMBER ...

Page 37: ...rents are a function of the distance size and composition of the conductor If the conductor is deflected toward the inductor as shown in Figure 8 1 more eddy currents will be generated Figure 8 1 Metal Deflection The eddy currents create their own magnetic field which opposes the original field generated by the inductor This effect reduces the effective inductance of the system resulting in an inc...

Page 38: ...he key parameters of the LC sensor include frequency effective parallel resistance RP and quality factor Q These parameters must be within the ranges as specified in the Sensor section of the Electrical Characteristics table Note that the effective RP and Q changes when the conductive target is in place L RS C Figure 8 3 LC Resonator The LC sensor frequency defined in Equation 3 must be between 1 ...

Page 39: ...l_Inductor_Designer tab of the LDC Calculations Tool 8 1 4 Defining Power On Timing The low power architecture of the LDC3114 makes it possible for the device to be active all the time When not being used the LDC3114 can operate in Low Power Mode with a single standby power button which typically consumes less than 10 µA If additional power saving is desired or in the rare event where a power on r...

Page 40: ...ble Ground 1 25 b10 Not Applicable Not Applicable Not Applicable Ground 2 5 b01 Not Applicable Not Applicable Not Applicable Ground 5 b00 Not Applicable Not Applicable Not Applicable Ground 10 Not Applicable b11 b0 b0 VDD 20 Not Applicable b10 b0 b0 VDD 40 Not Applicable b01 b0 b0 VDD 80 Not Applicable b00 b0 b0 VDD 160 Not Applicable Not Applicable b0 b1 VDD Continuous Not Applicable Not Applicab...

Page 41: ...ault 3 is the exponential LC divider that sets the approximate ranges for all channels and SENCYCn 0 to 31 default 4 is the linear sensor cycle scaler that fine tunes each individual channel Together they set the number of sensor oscillation cycles used to determine the sampling window For example if the LC sensor frequency is 9 2 MHz and it is desirable to get 1 ms sampling window then this can b...

Page 42: ...Triggering Threshold Every material shows some hysteresis when the material deforms then returns to the original state The amount of hysteresis is a function of material properties and physical parameters such as size and thickness This feature modifies the hysteresis of the button signal threshold according to different materials and various button shapes and sizes Hysteresis can be programmed in...

Page 43: ...t can be configured in Register NP_BASE_INC Address 0x15 In Low Power Mode use Equation 12 to determine the effective baseline increment per scan cycle BINCLP LPBI LP 2 BINC 9 12 where LPBI the Low Power Baseline Increment index that can be configured in Register LP_BASE_INC Address 0x13 As a result of baseline tracking a button press with a constant force only lasts for a finite amount of time Eq...

Page 44: ...g Factor Settings FTFn Setting Fast Tracking Factor b00 1 b01 4 b10 8 b11 16 Note When the continuous sampling rate using NPCS bit is set the baseline tracking increment is a fixed value 8 1 10 Mitigating False Button Detections The LDC3114 offers several algorithms that can mitigate false button detections due to mechanical non idealities associated with groups of buttons These are listed below 8...

Page 45: ... could happen when two buttons are physically very close to each other and pressing one causes a residual reaction on the other Buttons can be individually enabled to join the max win group by configuring Register BTPAUSE_MAXWIN Address 0x16 Time DATA Threshold 128 Hysteresis Button 0 Button 1 Intentional Press of Button 0 with coupled response of Button 1 Intentional Press of Button 1 OUTPUT with...

Page 46: ...cinity of one or more buttons Such metal deformation can be accidentally caused by pressing a neighboring button that does not have sufficient mechanical isolation The user can specify which buttons to join the anti deform group by configuring Register COMMON_DEFORM Address 0x1A 8 1 11 Reporting Interrupts for Button Presses Raw Data Ready and Error Conditions INTB the LDC3114 interrupt pin is ass...

Page 47: ...0 to 1 after the first button assertion OUT0 Pin INTB Pin 25 ms scan cycle 25 ms scan cycle Sampling 25 ms scan cycle Sampling Sampling OUT0 and INTB asserted OUT0 de asserted OUT1 asserted STATUS Register OUT1 Pin Button 0 pressed Button 1 released OUT1 and INTB de asserted Button 1 pressed Button 0 released Reading the Status Register clears the OUT_STATUS bit OUTn DQG 17 DUH SURJUDPPHG WR FWLYH...

Page 48: ...es them suitable for driving button sensors in consumer electronics such as mobile phones Most mobile phones today have three buttons along the edges namely the power button volume up and volume down On a typical smartphone the two volume buttons are next to each other so they may be susceptible to false detections such as simultaneous button presses To prevent such mis triggers they can be groupe...

Page 49: ...x26 2 Choose the sampling rate 80 40 20 10 5 2 5 1 25 or 0 625 SPS based on system power consumption requirement and configure Register NP_SCAN_RATE Address 0x0D or Register LP_SCAN_RATE Address 0x0F 3 Choose the button sampling window based on power consumption and noise requirements recommended 1 ms to 8 ms While a longer button sampling window provides better noise performance 1 ms is typically...

Page 50: ...ogrammed threshold default is 160 Look up the Gain Table to find the required gain setting 5 Enable special features to mitigate button interference if there is any in Registers BTPAUSE_MAXWIN TWIST COMMON_DEFORM Addresses 0x16 0x19 0x1A For more information on inductive touch system design including mechanical design and sensor electrical design refer to Inductive Touch System Design Guide 8 2 1 ...

Page 51: ...ld be placed as close as possible to the COM pin The COM signal should be tied to a small copper fill placed underneath the INn signals The INn signals should stay clear of other high frequency traces Each active channel needs to have an LC resonator connected to the corresponding INn pins The sensor capacitor should be placed within 10 mm of the corresponding INn pin and the inductor should be pl...

Page 52: ...Texas Instruments All trademarks are the property of their respective owners 11 5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD Texas Instruments recommends that all integrated circuits be handled with appropriate precautions Failure to observe proper handling and installation procedures can cause damage ESD damage can range from subtle performance degradation to co...

Page 54: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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