Copyright © 2017, Texas Instruments Incorporated
Board Setup Examples
14
SLAU711 – March 2017
Copyright © 2017, Texas Instruments Incorporated
HSDC Pro With Xilinx
®
KCU105
By default, the DAC GUI is configured to generate an FPGA reference clock as line rate/40. Since the
linerate is shown to be 3.6G the valid Multiplier line rate is only supported by x10 and x20 (refer to
). In order to support this mode, the settings of the LMK04828 registers needs to be changed.
From the GUI, navigate to the
LMK04828 Controls
tab. Under
Clock Outputs
, update the DCLK Divider to
"16" in the DAC GUI as shown in
Figure 11. DAC38J84EVM GUI DCLK Divider
Follow the procedure in
beginning with step number 4 to configure HSDC Pro and produce a
tone. Note that the data rate has changed to 1474.56 MSPS.
