Texas Instruments DS16EV5110, Operator'S Manual

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DS16EV5110
SNLS249M – FEBRUARY 2007 – REVISED APRIL 2013 www.ti.com
Electrical Characteristics — System Management Bus Interface
(1) (2)
Over recommended operating supply and temperature ranges unless other specified.
Symbol Parameter Conditions Min Typ Max Units
System Bus Interface — DC Specifications
V
IL
Data, Clock Input Low Voltage 0.8 V
V
IH
Data, Clock Input High Voltage 2.8 V
DD
V
I
PULLUP
Current through pull-up resistor or current VOL = 0.4V
10 mA
source
V
DD
Nominal Bus Voltage 3.0 3.6 V
I
LEAK-Bus
Input Leakage per bus segment See
(3)
—200 +200 µA
I
LEAK-Pin
Input Leakage per device pin —15 µA
C
I
Capacitance for SDA and SDC See
(3) (4)
10 pF
R
TERM
Termination Resistance V
DD3.3
(3) (4) (5)
1000 Ω
System Bus Interface Timing Specification
FSMB Bus Operating Frequency See
(6)
10 100 kHz
TBUF Bus Free Time Between Stop and Start
4.7 µs
Condition
THD:STA Hold Time After (Repeated) Start Condition. At I
PULLUP
, Max
4.0 µs
First CLK generated after this period.
TSU:STA Repeated Start Condition Setup Time 4.7 µs
TSU:STO Stop Condition Setup Time 4.0 µs
THD:DAT Data Hold Time 300 ns
TSU:DAT Data Setup Time 250 ns
T
TIMEOUT
Detect Clock Low Timeout See
(6)
25 35 ms
T
LOW
Clock Low Period 4.7 µs
T
HIGH
Clock High Period See
(6)
4.0 50 µs
T
LOW
:SEXT Cumulative Clock Low Extend Time (Slave See
(6)
2 ms
Device)
t
F
Clock/Data Fall Time See
(6)
300 ns
t
R
Clock/Data Rise Time See
(6)
1000 ns
t
POR
Time in which a device must be operational See
(6)
500 ms
after power-on reset
(1) Typical values represent most likely parametric norms at V
DD
= 3.3V, T
A
= 25°C, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes.
(3) Recommended value. Parameter not tested in production.
(4) Recommended maximum capacitance load per bus segment is 400pF.
(5) Maximum termination voltage should be identical to the device supply voltage.
(6) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
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