Texas Instruments DS16EV5110, Operator'S Manual

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DS16EV5110
SNLS249M – FEBRUARY 2007 – REVISED APRIL 2013 www.ti.com
PIN DESCRIPTIONS
Pin Name Pin Number I/O
(1)
, Type Description
HIGH SPEED DIFFERENTIAL I/O
C_IN − 1 I, CML Inverting and non-inverting TMDS Clock inputs to the equalizer. An on-chip 50 Ω terminating
C_IN+ 2 resistor connects C_IN+ to VDD and C_IN- to VDD.
D_IN0 − 4 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating
D_IN0+ 5 resistor connects D_IN0+ to VDD and D_IN0- to VDD.
D_IN1 − 8 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating
D_IN1+ 9 resistor connects D_IN1+ to VDD and D_IN1- to VDD.
D_IN2 − 11 I, CML Inverting and non-inverting TMDS Data inputs to the equalizer. An on-chip 50 Ω terminating
D_IN2+ 12 resistor connects D_IN2+ to VDD and D_IN2- to VDD.
C_OUT- 36 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
C_OUT+ 35
D_OUT0 − 33 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
32
D_OUT1– 29 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
28
D_OUT2 − 26 O, CML Inverting and non-inverting TMDS outputs from the equalizer. Open collector.
25
Equalization Control
BST_0 23 I, LVCMOS BST_0, BST_1, and BST_2 select the equalizer boost level for EQ channels. BST_0, BST_1,
BST_1 14 and BST_2 are internally pulled Low. See Table 2 .
BST_2 37
Device Control
EN 44 I, LVCMOS Enable Equalizer input. When held High, normal operation is selected. When held Low,
standby mode is selected. EN is internally pulled High. Signal is global to all Data and Clock
channels.
FEB 21 I, LVCMOS Force External Boost. When held High, the equalizer boost setting is controlled by the
BST_[0:2] pins. When held Low, the equalizer boost level is controlled through the SMBus
(see
Table 1 ) control pins. FEB is internally pulled High.
SD 45 O, LVCMOS Equalizer Clock Channel Signal Detect Output. Produces a High when signal is detected.
POWER
V
DD
3, 6, 7, Power V
DD
pins should be tied to the V
DD
plane through a low inductance path. A 0.1µF bypass
10, 13, capacitor should be connected between each V
DD
pin to the GND planes.
15, 46
GND 22, 24, GND Ground reference. GND should be tied to a solid ground plane through a low impedance
27, 30, path.
31, 34
Exposed Pad DAP GND The exposed pad at the center of the package must be connected to the ground plane.
System Management Bus (SMBus) Interface Control Pins
SDA 18 IO, LVCMOS SMBus Data Input / Output. Internally pulled High to 3.3V with High-Z pull up.
SDC 17 I, LVCMOS SMBus Clock Input. Internally pulled High to 3.3V with High-Z pull up.
CS 16 I, LVCMOS SMBus Chip select. When held High, the equalizer SMBus register is enabled. When held
Low, the equalizer SMBus register is disabled. CS is internally pulled Low. CS is internally
gated with SDC.
Other
Reserv 19, 20, 38, Reserved. Do not connect.
39, 40,41,
42, 43, 47,
48
(1) Note: I = Input,O = Output, IO =Input/Output,
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