SNLS249M – FEBRUARY 2007 – REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Supply Voltage (V
DD
)
-0.5V to +4.0V
LVCMOS Input Voltage
-0.5V + 4.0V
LVCMOS Output Voltage
-0.5V to 4.0V
CML Input/Output Voltage
-0.5V to 4.0V
Junction Temperature
+150°C
Storage Temperature
-65°C to +150°C
Lead Temperature (Soldering, 5 sec.)
+260°C
HBM, 1.5 k
Ω
, 100 pF
>8 kV
ESD Rating
CML Inputs
>10 kV
Thermal Resistance
θ
JA
, No Airflow
30°C/W
(1)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are ensured for a junction temperature range of –40°C to +125°C. Models are validated to Maximum Operating
Voltages only.
(2)
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions
(1) (2)
Min
Typ
Max
Units
Supply Voltage (V
DD
to GND)
3.0
3.3
3.6
V
Ambient Temperature
-40
25
+85
°C
(1)
Typical values represent most likely parametric norms at V
DD
= 3.3V, T
A
= 25°C, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
(2)
The
tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes.
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
(1) (2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS DC SPECIFICATIONS
I
IH-PU
High Level Input Leakage Current
LVCMOS pins with internal pull-up
-10
+10
μ
A
resistors
I
IH-PD
High Level Input Leakage Current
LVCMOS pins with internal pull-
80
105
μ
A
down resistors
I
IL-PU
Low Level Input Leakage Current
LVCMOS pins with internal pull-up
-20
-10
μ
A
resistors
I
IL-PD
Low Level Input Leakage Current
LVCMOS pins with internal pull-
-10
+10
μ
A
down resistors
V
IH
High Level Input Voltage
2.0
VDD
V
V
IL
Low Level Input Voltage
0
0.8
V
V
OH
High Level Output Voltage
SD Pin, I
OH
= -3mA
2.4
V
V
OL
Low Level Output Voltage
SD Pin, I
OL
= 3mA
0.4
V
POWER
PD
Power Dissipation
EN = High, Device Enabled
475
700
mW
EN = Low, Power Down Mode
70
mW
(1)
Typical values represent most likely parametric norms at V
DD
= 3.3V, T
A
= 25°C, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
(2)
The
tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes.
4
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