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DVI / HDMI 

Source

text

DS16EV5110

DeS / Display 

Controller

DVI / HDMI Sink

20m 28 AWG DVI / HDMI Cable

DS16EV5110

www.ti.com

SNLS249M – FEBRUARY 2007 – REVISED APRIL 2013

DS16EV5110 Video Equalizer (3D+C) for DVI, HDMI Sink-Side Applications

Check for Samples:

DS16EV5110

1

FEATURES

APPLICATIONS

2

8 Levels of Equalization Settable by 3 Pins or

Sink-Side Video Applications

Through the SMBus Interface

Projectors

DC-Coupled Inputs and Outputs

High Definition Displays

Optimized for Operation From 250 Mbps to
2.25 Gbps in Support of UXGA, 480 I/P, 720 I/P,

DESCRIPTION

1080 I, and 1080 P With 8, 10, and 12-Bit Color

The

DS16EV5110

is

a

multi-channel

equalizer

Depth Resolutions

optimized

for

video

cable

extension

sink-side

applications. It operates between 250Mbps and

Two DS16EV5110 Devices Support DVI/HDMI

2.25Gbps with common applications at 1.65Gbps and

Dual Link

2.25Gbps (per data channel). It contains three

DVI 1.0, and HDMI 1.3a Compatible TMDS

Transition-Minimized Differential Signaling (TMDS)

Interface

data channels and one clock channel as commonly
found

in

DVI

and

HDMI

cables.

It

provides

Clock Channel Signal Detect (LOS)

compensation for skin-effect and dielectric losses, a

Enable for Power Savings Standby Mode

common phenomenon when transmitting video on

System Management Bus (SMBus) Provides

commercially available high definition video cables.

Control of Boost, Output Amplitude, Enable,

The inputs conform to DVI and HDMI requirements

and Clock Channel Signal Detect Threshold

and

features

programmable

levels

of

input

Low Power Consumption: 475mW (Typical)

equalization.

The

programmable

levels

of

0.13 UI Total Jitter at 1.65 Gbps Including

equalization provide optimal signal boost and reduces
inter-symbol interference. Eight levels of boost are

Cable

selectable via a pin interface or by the optional

Single 3.3V Power Supply

System Management Bus.

Small 7mm x 7mm, 48-Pin Leadless WQFN

The clock channel is optimized for clock rates of up to

Package

225 MHz and features a signal detect circuit. To

-40°C to +85°C Operating Temperature Range

maximize noise immunity, the DS16EV5110 features

Extends TMDS Cable Reach Over:

a signal detector with programmable thresholds. The
threshold

is

adjustable

through

a

System

1. > 40 Meters 24 AWG DVI Cable (1.65Gbps)

Management Bus (SMBus) interface.

2. > 20 Meters 28 AWG DVI Cable (1.65Gbps)

The DS16EV5110 also provides support for system

3. >

20

Meters

Cat5/Cat5e/Cat6

Cables

power management via output enable controls.

(1.65Gbps)

Additional controls are provided via the SMBus

4. >

20

Meters

28

AWG

HDMI

Cables

enabling customization and optimization for specific

(2.25Gbps)

applications requirements. These controls include
programmable features such as output amplitude and
boost controls as well as system level diagnostics.

Typical Application

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Summary of Contents for DS16EV5110

Page 1: ...he programmable levels of 0 13 UI Total Jitter at 1 65 Gbps Including equalization provide optimal signal boost and reduces inter symbol interference Eight levels of boost are Cable selectable via a pin interface or by the optional Single 3 3V Power Supply System Management Bus Small 7mm x 7mm 48 Pin Leadless WQFN The clock channel is optimized for clock rates of up to Package 225 MHz and features...

Page 2: ...44 I LVCMOS Enable Equalizer input When held High normal operation is selected When held Low standby mode is selected EN is internally pulled High Signal is global to all Data and Clock channels FEB 21 I LVCMOS Force External Boost When held High the equalizer boost setting is controlled by the BST_ 0 2 pins When held Low the equalizer boost level is controlled through the SMBus see Table 1 contro...

Page 3: ...T2 D_OUT1 D_OUT1 D_OUT0 D_OUT0 C_OUT C_OUT VDD VDD VDD VDD GND GND GND GND VDD VDD GND GND BST_1 BST_0 CS SDC SDA Reserv VDD SD EN Reserv Reserv Reserv Reserv Reserv Reserv Reserv BST_2 Reserv FEB Reserv DS16EV5110 www ti com SNLS249M FEBRUARY 2007 REVISED APRIL 2013 Connection Diagram TOP VIEW Not to Scale Copyright 2007 2013 Texas Instruments Incorporated Submit Documentation Feedback 3 Product ...

Page 4: ...85 C 1 Typical values represent most likely parametric norms at VDD 3 3V TA 25 C and at the Recommended Operation Conditions at the time of product characterization and are not ensured 2 The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and or Not...

Page 5: ... Latency 350 ps OUTPUT JITTER TJ1 Total Jitter at 1 65 Gbps 20m 28 AWG STP DVI Cable Data Paths 0 13 0 17 UIP P EQ Setting 0x04 PRBS7 4 5 6 TJ2 Total Jitter at 2 25 Gbps 20m 28 AWG STP DVI Cable Data Paths 0 2 UIP P EQ Setting 0x04 PRBS7 4 5 6 TJ3 Total Jitter at 165 MHz Clock Paths 0 165 UIP P Clock Pattern 4 5 6 TJ4 Total Jitter at 225 MHz Clock Paths 0 165 UIP P Clock Pattern 4 5 6 RJ Random Ji...

Page 6: ...ns TSU DAT Data Setup Time 250 ns TTIMEOUT Detect Clock Low Timeout See 6 25 35 ms TLOW Clock Low Period 4 7 µs THIGH Clock High Period See 6 4 0 50 µs TLOW SEXT Cumulative Clock Low Extend Time Slave See 6 2 ms Device tF Clock Data Fall Time See 6 300 ns tR Clock Data Rise Time See 6 1000 ns tPOR Time in which a device must be operational See 6 500 ms after power on reset 1 Typical values represe...

Page 7: ...WG DVI HDMI Cable VDD TPC TPB TPA SMA SMA SMA SMA SMA SMA SMA SMA Coax Coax Coax Coax Coax Coax Coax Coax Clk Clk Data0 Data0 Data1 Data1 Data2 Data2 SP tBUF tHD STA tLOW tR tHD DAT tHIGH tF tSU DAT tSU STA ST SP tSU STO SDC SDA CS tSU CS ST DS16EV5110 www ti com SNLS249M FEBRUARY 2007 REVISED APRIL 2013 TIMING DIAGRAMS Figure 1 SMBus Timing Diagram Figure 2 Test Setup Diagram for Jitter Measureme...

Page 8: ...ime exceeding tBUF from the last detected STOP condition or if they are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state SMBus Transactions The device supports WRITE and READ transactions See Register Description table for register address type Read Write Read Only default value and function information Writing a Register To write a regist...

Page 9: ...ed Enable 0 Enable BC for CH0 0 Enable Individual 1 Disable 000 Min Boost 1 Disable Channel D_IN0 001 C_IN Boost 010 Control 011 for 100 C_IN 101 D_IN0 110 111 Max Boost Individual 0x04 0x77 RW EN Int Boost Control EN Int Boost Control Channel 0 Enable BC for CH2 0 Enable BC for CH1 Boost 1 Disable 000 Min Boost 1 Disable 000 Min Boost Control D_IN2 001 D_IN1 001 for 010 010 D_IN1 011 011 D_IN2 10...

Page 10: ...ed the boost settings are controlled by the Boost Set pins BST_ 0 2 The range of boost settings provided enables the DS16EV5110 to address a wide range of transmission line path loss scenarios enabling support for a variety of data rates and formats Table 2 EQ Boost Control Table Control Via SMBus Control Via Pins EQ Boost Setting at BC_2 BC_1 BC_0 BST_2 BST_1 825 MHz dB FEB 0 BST_0 TYP FEB 1 000 ...

Page 11: ...tes the presence of a signal that has exceeded a specified threshold value called SD_ON A logic Low means that the clock signal has fallen below a threshold value called SD_OFF These values are programmed via the SMBus Table 1 If not programmed via the SMBus the thresholds take on the default values for the SD_OFF and SD_ON values as indicated in Table 4 The Signal Detect threshold values can be c...

Page 12: ...NDBY mode if no clock signal is present STANDBY mode can be implemented by connecting the Signal Detect SD pin to the external LVCMOS Enable EN pin In order for this option to function properly REG07 0 should be set to a 0 default value If the clock signal applied to the clock channel input swings above the SD_ON threshold specified in the threshold register via the SMBus then the SD pin is assert...

Page 13: ...ath It is also not recommneded to enable the DS16EV5110 CML outputs without a load attached Figure 5 DS16EV5110 Sink side application The DS16EV5110 may also be used in certain Source side application with certain restrictions The DS16EV5110 CML outputs will not meet the VOFF parameter required by the HDMI Compliance Test Specification v1 3b when the DS16EV5110 is powered off and the sink device i...

Page 14: ...ease note that the Electrical Characteristics specified in this document have not been tested for and are not ensured for 2 25 Gbps operation DC COUPLED DATA PATHS AND DVI HDMI COMPLIANCE The DS16EV5110 is designed to support TMDS differential pairs with DC coupled transmission lines It contains integrated termination resistors 50Ω pulled up to VDD at the input stage and open collector outputs for...

Page 15: ...han 20m Figure 8 shows the cable extension and jitter reduction obtained with the use of the equalizer Table 6 lists the various gain settings used versus cable length recommendations Figure 8 Equalized vs Unequalized Jitter Performance Over 28 AWG DVI HDMI Cable UTP UNSHIELDED TWIST PAIRS CABLES The DS16EV5110 can be used to extend the length of UTP cables such as Cat5 Cat5e and Cat6 to distances...

Page 16: ...inted circuit board All traces of TMDS differential inputs and outputs must be equal in length to minimize intra pair skew WQFN FOOTPRINT RECOMMENDATIONS See application note AN 1187 SNOA401 for additional information on WQFN packages footprint and soldering information POWER SUPPLY BYPASSING Two approaches are recommended to ensure that the DS16EV5110 is provided with an adequate power supply Fir...

Page 17: ...ww ti com SNLS249M FEBRUARY 2007 REVISED APRIL 2013 Figure 10 Equivalent Output Structure Figure 11 Equivalent Input Structure Copyright 2007 2013 Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links DS16EV5110 ...

Page 18: ...t Signal after 20m of Cat5 Cable at Figure 14 Output Signal after 30m of 28 AWG DVI Cable at 1 65 Gbps 0x06 Setting 750 Mbps 0x06 Setting Figure 15 Output Signal after 0 3m of 28 AWG DVI Cable at Figure 16 Output Signal after 20m of 28 AWG HDMI Cable 1 65 Gbps 0x04 Setting at 2 25 Gbps 0x06 Setting 18 Submit Documentation Feedback Copyright 2007 2013 Texas Instruments Incorporated Product Folder L...

Page 19: ...D APRIL 2013 REVISION HISTORY Changes from Revision L April 2013 to Revision M Page Changed layout of National Data Sheet to TI format 18 Copyright 2007 2013 Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links DS16EV5110 ...

Page 20: ...Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame reta...

Page 21: ...PQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant DS16EV5110SQ NOPB WQFN NJU 48 250 178 0 16 4 7 3 7 3 1 3 12 0 16 0 Q1 DS16EV5110SQX NOPB WQFN NJU 48 2500 330 0 16 4 7 3 7 3 1 3 12 0 16 0 Q1 PACKAGE MATERIALS INFORMATION www ti com 12 Feb 2015 Pack Materials Page 1 ...

Page 22: ...age Type Package Drawing Pins SPQ Length mm Width mm Height mm DS16EV5110SQ NOPB WQFN NJU 48 250 213 0 191 0 55 0 DS16EV5110SQX NOPB WQFN NJU 48 2500 367 0 367 0 38 0 PACKAGE MATERIALS INFORMATION www ti com 12 Feb 2015 Pack Materials Page 2 ...

Page 23: ...MECHANICAL DATA NJU0048D www ti com SQA48D Rev A ...

Page 24: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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