Contents
Preface
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6
1
Introduction
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9
1.1
Purpose of the Peripheral
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9
1.2
Features
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9
1.3
Functional Block Diagram
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9
1.4
Industry Standard(s) Compliance Statement
...............................................................
10
2
Peripheral Architecture
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11
2.1
Clock Control
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11
2.2
Memory Map
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11
2.3
Signal Descriptions
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11
2.4
Protocol Description(s)
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13
2.5
Memory Width and Byte Alignment
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18
2.6
Address Mapping
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19
2.7
DDR2 Memory Controller Interface
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22
2.8
Refresh Scheduling
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25
2.9
Self-Refresh Mode
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26
2.10
Reset Considerations
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26
2.11
DDR2 SDRAM Memory Initialization
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27
2.12
Interrupt Support
................................................................................................
28
2.13
EDMA Event Support
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28
2.14
Emulation Considerations
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28
3
Using the DDR2 Memory Controller
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29
3.1
Connecting the DDR2 Memory Controller to DDR2 SDRAM
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29
3.2
Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications
.............
33
4
DDR2 Memory Controller Registers
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36
4.1
Module ID and Revision Register (MIDR)
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37
4.2
DDR2 Memory Controller Status Register (DMCSTAT)
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37
4.3
SDRAM Configuration Register (SDCFG)
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38
4.4
SDRAM Refresh Control Register (SDRFC)
................................................................
40
4.5
SDRAM Timing 1 Register (SDTIM1)
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41
4.6
SDRAM Timing 2 Register (SDTIM2)
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43
4.7
Burst Priority Register (BPRIO)
...............................................................................
44
4.8
DDR2 Memory Controller Control Register (DMCCTL)
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45
Appendix A Revision History
.............................................................................................
46
SPRUEK5A – October 2007
Table of Contents
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