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REFR

DDR_CLK
DDR_CLK

DDR_CS

DDR_CKE

DDR_RAS

DDR_WE

DDR_DQM[3:0]

DDR_CAS

DDR_BA[2:0]

DDR_A[13:0]

2.4.3

Activation (ACTV)

ACTV

BANK

ROW

DDR_CLK
DDR_CLK

DDR_CS

DDR_CKE

DDR_RAS

DDR_WE

DDR_DQM[3:0]

DDR_CAS

DDR_BA[2:0]

DDR_A[13:0]

Peripheral Architecture

Figure 4. Refresh Command

The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to
a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or
writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of A[12:0] selects
the row. When the DDR2 memory controller issues an ACTV command, a delay of t

RCD

is incurred before

a read or write command is issued.

Figure 5

shows an example of an ACTV command. Reads or writes to

the currently active row and bank of memory can achieve much higher throughput than reads or writes to
random areas because every time a new row is accessed, the ACTV command must be issued and a
delay of t

RCD

incurred.

Figure 5. ACTV Command

SPRUEK5A – October 2007

DSP DDR2 Memory Controller

15

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Summary of Contents for DM648 DSP

Page 1: ...TMS320DM647 DM648 DSP DDR2 Memory Controller User s Guide Literature Number SPRUEK5A October 2007 ...

Page 2: ...2 SPRUEK5A October 2007 Submit Documentation Feedback ...

Page 3: ...8 2 13 EDMA Event Support 28 2 14 Emulation Considerations 28 3 Using the DDR2 Memory Controller 29 3 1 Connecting the DDR2 Memory Controller to DDR2 SDRAM 29 3 2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications 33 4 DDR2 Memory Controller Registers 36 4 1 Module ID and Revision Register MIDR 37 4 2 DDR2 Memory Controller Status Register DMCSTAT 37 4 3 SDRAM Configura...

Page 4: ...ank Access 22 15 DDR2 Memory Controller FIFO Block Diagram 23 16 DDR2 Memory Controller Reset Block Diagram 26 17 Connecting to Two 16 Bit DDR2 SDRAM Devices 30 18 Connecting to a Single 16 Bit DDR2 SDRAM Device 31 19 Connecting to Two 8 Bit DDR2 SDRAM Devices 32 20 Module ID and Revision Register MIDR 37 21 DDR2 Memory Controller Status Register DMCSTAT 37 22 SDRAM Configuration Register SDCFG 38...

Page 5: ...TIM1 Configuration 34 15 SDTIM2 Configuration 35 16 DMCCTL Configuration 35 17 DDR2 Memory Controller Registers 36 18 Module ID and Revision Register MIDR Field Descriptions 37 19 DDR2 Memory Controller Status Register DMCSTAT Field Descriptions 37 20 SDRAM Configuration Register SDCFG Field Descriptions 38 21 SDRAM Refresh Control Register SDRFC Field Descriptions 40 22 SDRAM Timing 1 Register SD...

Page 6: ...nstruction Set Reference Guide describes the CPU architecture pipeline instruction set and interrupts for the TMS320C64x and TMS320C64x digital signal processors DSPs of the TMS320C6000 DSP family The C64x C64x DSP generation comprises fixed point devices in the C6000 DSP platform The C64x DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set SPRUEK5 TMS320...

Page 7: ...e The PCI port interfaces to the DSP via the enhanced DMA EDMA controller This architecture allows for both PCI master and slave transactions while keeping the EDMA channel resources available for other applications SPRUEL5 TMS320DM647 DM648 DSP Host Port Interface UHPI User s Guide describes the host port interface HPI in the TMS320DM647 DM648 Digital Signal Processor DSP The HPI is a parallel po...

Page 8: ...l processing for digital media applications The subsystem acts as the overall system controller responsible for handling many system functions such as system level initialization configuration user interface user command execution connectivity functions and overall system control SPRUF57 TMS320DM647 DM648 DSP 3 Port Switch 3PSW Ethernet Subsystem User s Guide describes the operation of the 3 port ...

Page 9: ...RAM 256 Mbyte memory space Data bus width of 32 or 16 bits CAS latencies 2 3 4 and 5 Internal banks 1 2 4 and 8 Burst length 8 Burst type sequential 1 CE signal Page sizes 256 512 1024 and 2048 SDRAM auto initialization Self refresh mode Prioritized refresh Programmable refresh rate and backlog counter Programmable timing parameters The DDR2 memory controller is the main interface to external DDR2...

Page 10: ...r peripherals EDMA Boot configuration Switched central resource PLL2 L2 memory controller controller memory External controller DMA Master DMA Slave Cache control Bandwidth management Memory protection 1 4 Industry Standard s Compliance Statement Introduction Figure 1 DDR2 Memory Controller Block Diagram The DDR2 memory controller is compliant with the JESD79D 2A DDR2 SDRAM standard with the excep...

Page 11: ...CLK The frequency of DDR_CLK can be determined by using the following formula DDR_CLK frequency PLL2 input clock frequency 20 2 PLL2 input clock frequency 10 The second output clock of the DDR2 memory controller DDR_CLK is the inverse of DDR_CLK For more information on the PLL2 see the device specific data manual Please see the device specific data manual for information describing the device memo...

Page 12: ... clock outputs DDR_CLK DDR_CKE Clock enable used for self refresh mode DDR_CAS Active low column address strobe DDR_RAS Active low row address strobe DDR_WE Active low write enable DDR_DQS 3 0 Differential data strobe bidirectional signals DDR_DQS 3 0 DDR_ODT 1 0 On die termination signals to external DDR2 SDRAM These pins are reserved for future use and should not be connected to the DDR2 SDRAM N...

Page 13: ...e operation WRT with Inputs the starting column address and begins the write operation The write operation is followed by a autoprecharge precharge Table 3 Truth Table for DDR2 SDRAM Commands DDR2 SDRAM Signals CKE CS RAS CAS WE BA 2 0 A 13 11 9 0 A10 DDR_CKE DDR2 Memory Previous DDR_BA 2 0 Controller Signals Cycles Current Cycle DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A 13 11 9 0 DDR_A 10 ACTV H 1 H L ...

Page 14: ...y controller only issues MRS and EMRS commands during the DDR2 memory controller initialization sequence See Section 2 11 for more information Figure 3 DDR2 MRS and EMRS Command The DDR2 memory controller issues refresh commands to the DDR2 SDRAM device Figure 4 REFR is automatically preceded by a DCAB command ensuring the deactivation of all CE spaces and banks selected Following the DCAB command...

Page 15: ...ng future accesses reads or writes with minimum latency The value of DDR_BA 2 0 selects the bank and the value of A 12 0 selects the row When the DDR2 memory controller issues an ACTV command a delay of tRCD is incurred before a read or write command is issued Figure 5 shows an example of an ACTV command Reads or writes to the currently active row and bank of memory can achieve much higher through...

Page 16: ...ory controller or following the initialization sequence DDR2 SDRAMs also require this cycle prior to a refresh REFR and mode set register commands MRS and EMRS During a DCAB command DDR_A 10 is driven high to ensure the deactivation of all banks Figure 6 shows the timing diagram for a DCAB command Figure 6 DCAB Command The DEAC command closes a single bank of memory specified by the bank select si...

Page 17: ...CAS latency is three cycles in Figure 8 Read latency is equal to CAS latency plus additive latency The DDR2 memory controller always configures the memory to have an additive latency of 0 so read latency equals CAS latency Since the default burst size is 8 the DDR2 memory controller returns 8 pieces of data for every read command If additional accesses are not pending to the DDR2 memory controller...

Page 18: ...ng for a write on the DDR2 memory controller If the transfer request is for less than 8 words depending on the scheduling result and the pending commands the DDR2 memory controller can Mask out the additional data using DDR_DQM outputs Terminate the write burst and start a new write burst The DDR2 memory controller does not perform the DEAC command until page information becomes invalid Figure 9 D...

Page 19: ...ription IBANK Defines the number of internal banks on the external DDR2 memory 0 1 bank 1h 2 banks 2h 4 banks 3h 8 banks PAGESIZE Defines the page size of each page of the external DDR2 memory 0 256 words requires 8 column address bits 1h 512 words requires 9 column address bits 2h 1024 words requires 10 column address bits 3h 2048 words requires 11 column address bits Figure 11 and Figure 12 show...

Page 20: ...ress bits BE byte enable bits Figure 12 Logical Address to DDR2 SDRAM Address Map for 16 bit SDRAM SDCFG Bit Logical Address IBANK PAGESIZE 31 28 27 26 25 24 23 22 21 16 15 14 13 12 11 10 9 8 1 0 0 X X X X X X nrb 14 1 ncb 8 1 0 X X X X X nrb 14 nbb 1 ncb 8 2 0 X X X X nrb 14 nbb 2 ncb 8 3 0 X X X nrb 14 nbb 3 ncb 8 0 1 X X X X X nrb 14 ncb 9 1 1 X X X X nrb 14 nbb 1 ncb 9 2 1 X X X nrb 14 nbb 2 n...

Page 21: ...ing across banks while remaining on the same row page the DDR2 memory controller maximizes the number of activated banks for a linear access This results in the maximum number of open pages when performing a linear access being equal to the number of banks Note that the DDR2 memory controller never opens more than one page per bank Ending the current access is not a condition that forces the activ...

Page 22: ... DDR2 SDRAM device the DDR2 memory controller makes use of a command FIFO a write FIFO a read FIFO and command and data schedulers Table 6 describes the purpose of each FIFO Figure 15 shows the block diagram of the DDR2 memory controller FIFOs Commands write data and read data arrive at the DDR2 memory controller parallel to each other The same peripheral bus is used to write and read data from ex...

Page 23: ... the external memory For each master the DDR2 memory controller reorders the commands based on the following rules Selects the oldest command A read command is advanced before an older write command if the read is to a different block address 2048 bytes and the read priority is equal to or greater than the write priority Note Most masters issue commands on a single priority level Also the EDMA tra...

Page 24: ...est Request to enter self refresh mode The following results from the above scheduling algorithm All writes from a single master will complete in order All reads from a single master will complete in order From the same master any read to the same location or within 2048 bytes as a previous write will complete in order The reordering and scheduling rules listed above may lead to command starvation...

Page 25: ...roller performs a REFR command the backlog counter decrements by 1 This means the refresh backlog counter records the number of REFR commands the DDR2 memory controller currently has outstanding The DDR2 memory controller issues REFR commands based on the level of urgency The level of urgency is defined in Table 7 Whenever the refresh level of urgency is reached the DDR2 memory controller issues a...

Page 26: ...lf refresh command was issued The value of T_CKE is defined in the SDRAM timing 2 register SDTIM2 After exiting from the self refresh state the DDR2 memory controller will not immediately start using commands Instead it will wait T_SXNR 1 clock cycles before issuing non read commands and T_SXRD 1 clock cycles before issuing read commands The SDRAM timing 2 register SDTIM2 programs the values of T_...

Page 27: ...arting the initialization sequence The DDR2 memory controller initializes the mode register and extended mode register 1 of the memory device with the values shown on Table 9 and Table 10 The DDR2 SDRAM extended mode registers 2 and 3 are configured with a value of 0h Table 9 DDR2 SDRAM Mode Register Configuration Mode Mode Register Register Bit Field Init Value Description 12 Power down Mode 0 Ac...

Page 28: ...ytes in the SDRAM configuration register SDCFG Using this approach data and commands stored in the DDR2 memory controller FIFOs are not lost and the DDR2 memory controller ensures read and write commands are completed before starting the initialization sequence Perform the following steps to start the initialization sequence 1 Set the BOOT_UNLOCK bit in the SDRAM configuration register SDCFG 2 Wri...

Page 29: ...RAM devices All DDR2 SDRAM devices must be complaint to the JESD79D 2A standard Not all of the memory topologies shown may be supported by your device See the device specific data manual for more information Printed circuit board PCB layout rules and connection requirements between the DSP and the memory device exist and are described in a separate document See the device specific data manual for ...

Page 30: ...GATE0 A DDR2 memory controller ODT DDR_DQS2 DDR_DQS3 memory x16 bit LDQS A 12 0 VREF ODT DQ 15 0 UDQS BA 2 0 UDQS LDQS LDM UDM RAS CAS WE CS CKE CK CK DDR2 VREF DDR_ODT0 DDR_ODT1 DDR_DQGATE1 A DDR_DQGATE2 A DDR_DQGATE3 A Using the DDR2 Memory Controller Figure 17 Connecting to Two 16 Bit DDR2 SDRAM Devices A These pins are used as a timing reference during memory reads For routing rules see the de...

Page 31: ...Q 15 0 ODT VREF LDQS UDQS DDR2 memory x16 bit VREF DDR2 memory controller DDR_ODT1 DDR_DQGATE0 A DDR_DQGATE1 A DDR_DQGATE2 A DDR_DQGATE3 A Using the DDR2 Memory Controller Figure 18 Connecting to a Single 16 Bit DDR2 SDRAM Device A These pins are used as a timing reference during memory reads For routing rules see the device specific data manual SPRUEK5A October 2007 DSP DDR2 Memory Controller 31 ...

Page 32: ...T DDR_ODT0 DDR_ODT1 DDR_DQS1 memory x8 bit DQS A 13 0 VREF ODT DQ 7 0 RDQS BA 2 0 RDQS DQS DM RAS CAS WE CS CKE CK CK DDR2 VREF RDQS DDR_DQGATE0 A DDR_DQGATE1 A DDR_DQGATE2 A DDR_DQGATE3 A Using the DDR2 Memory Controller Figure 19 Connecting to Two 8 Bit DDR2 SDRAM Devices A These pins are used as a timing reference during memory reads For routing rules see the device specific data manual DSP DDR...

Page 33: ...gure the DDR2 memory controller to match the data bus width CAS latency number of banks and page size of the attached DDR2 memory Table 11 shows the resulting SDCFG configuration Note that the value of the TIMUNLOCK field is dependent on whether or not it is desirable to unlock SDTIM1 and SDTIM2 The TIMUNLOCK bit should only be set to 1 when the SDTIM1 and SDTIM2 needs to be updated Table 11 SDCFG...

Page 34: ...gister field name and corresponding DDR2 data sheet parameter name along with the data sheet value These tables also provide a formula to calculate the register field value and displays the resulting calculation Each of the equations include a minus 1 because the register fields are defined in terms of DDR2 clock cycles minus 1 See Section 4 5 and Section 4 6 for more information Table 14 SDTIM1 C...

Page 35: ...SXRD 1 199 command T_RTP tRTP Read to precharge command 7 5 nS tRTP fDDR2_CLK 1 1 delay T_CKE tCKE CKE minimum pulse width 3 tCK cycles tCKE 1 2 The DDR2 memory controller control register DMCCTL contains a read latency RL field that helps the DDR2 memory controller determine when to sample read data The RL field should be programmed to a value equal to CAS latency plus 1 For example if a CAS late...

Page 36: ...ection 00h MIDR Module ID and Revision Register Section 4 1 04h DMCSTAT DDR2 Memory Controller Status Register Section 4 2 08h SDCFG SDRAM Configuration Register Section 4 3 0Ch SDRFC SDRAM Refresh Control Register Section 4 4 10h SDTIM1 SDRAM Timing 1 Register Section 4 5 14h SDTIM2 SDRAM Timing 2 Register Section 4 6 20h BPRIO Burst Priority Register Section 4 7 E4h DMCCTL DDR2 Memory Controller...

Page 37: ...0 R 0x1 R 0x0 15 3 2 1 0 Reserved IFRDY Reserved R 0x0 R 0x0 R 0x0 LEGEND R W Read Write R Read only n value after reset Table 19 DDR2 Memory Controller Status Register DMCSTAT Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved The value always should be written as 0 write of 1 results an error in functionality 30 Reserved 1 Reserved The reserved bit location is always read as 1...

Page 38: ... bits at their default values 23 BOOT_UNLOCK Boot unlock bit Controls write access to bits 16 through 22 of this register 0 Writes to bits 22 16 of this register are not permitted 1 Writes to bits 22 16 of this register are allowed 22 19 Reserved Reserved Writes to this register must keep these bits at their default value 18 DDR_DRIVE DDR2 SDRAM drive strength This bit is used to select the drive ...

Page 39: ...ide connected SDRAM devices A write to this bit will cause the DDR2 Memory Controller to start the SDRAM initialization sequence Values 4 7 are reserved for this field 0 One bank SDRAM devices 1 Two banks SDRAM devices 2 Four banks SDRAM devices 3 Eight banks SDRAM devices 3 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 2 0 PAGESIZE Pag...

Page 40: ...ield Value Description 31 SR Self refresh bit Writing a 1 to this bit will cause connected SDRAM devices to be place into Self Refresh mode and the DDR2 Memory Controller to enter the Self Refresh state 0 Exit self refresh mode 1 Enter self refresh mode 30 Reserved Reserved Writes to this register must keep this field at its default value 29 16 Reserved Reserved The reserved bit location is always...

Page 41: ... read or write command minus 1 The value for these bits can be derived from the trcd AC timing parameter in the DDR2 memory data sheet Calculate using the formula T_RCD trcd DDR_CLK 1 18 16 T_WR These bits specify the minimum number of DDR_CLK cycles from the last write transfer to a precharge command minus 1 The value for these bits can be derived from the twr AC timing parameter in the DDR2 memo...

Page 42: ...0 T_WTR These bits specify the minimum number of DDR_CLK cycles from the last write to a read command minus 1 The value for these bits can be derived from the twtr AC timing parameter in the DDR2 memory data sheet Calculate using this formula T_WTR twtr DDR_CLK 1 42 DSP DDR2 Memory Controller SPRUEK5A October 2007 Submit Documentation Feedback ...

Page 43: ...R2 SDRAM T_ODT must be less than the CAS latency minus one Calculate using this formula T_ODT CAS latency taond 1 22 16 T_SXNR 0 7Fh These bits specify the minimum number of DDR_CLK cycles from a self_refresh exit to any other command except a read command minus 1 The value for these bits can be derived from the tSXNR AC timing parameter in the DDR2 data sheet Calculate using this formula T_SXNR t...

Page 44: ...rity Register BPRIO 31 16 Reserved R 0 15 8 7 0 Reserved PRIO_RAISE R 0 R W 0xFF LEGEND R W Read Write R Read only n value after reset Table 24 Burst Priority Register BPRIO Field Descriptions Bit Field Value Description 31 8 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 7 0 PRIO_RAISE Number of memory transfers after which the DDR2 mem...

Page 45: ...d Writes to this register must keep this field at its default value 15 6 Reserved Reserved Writes to this register must keep this field at its default value 5 IFRESET DDR2 memory controller interface logic reset The interface logic controls the signals used to communicate with DDR2 SDRAM devices This bit resets the interface logic The status of this interface logic is shown on the DDR2 memory cont...

Page 46: ... manual Section 2 3 Changed fourth bullet Figure 2 Changed Figure 2 Figure 3 Changed Figure 3 Figure 4 Changed Figure 4 Figure 5 Changed Figure 5 Figure 6 Changed Figure 6 Figure 7 Changed Figure 7 Section 2 4 5 Changed third sentence first paragraph Figure 8 Changed Figure 8 Figure 9 Changed Figure 9 Figure 17 Changed Figure 17 Figure 18 Changed Figure 18 Figure 19 Changed Figure 19 46 Revision H...

Page 47: ...ice and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyer...

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