Registers
612
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.60 VPDMA_int2_channel3_int_mask Register (offset = FCh) [reset = 0h]
VPDMA_int2_channel3_int_mask is shown in
and described in
Figure 1-360. VPDMA_int2_channel3_int_mask Register
31
30
29
28
27
26
25
24
INT_MASK_VIP2_MU
LT_PORTB_SRC3
INT_MASK_VIP2_MU
LT_PORTB_SRC2
INT_MASK_VIP2_MU
LT_PORTB_SRC1
INT_MASK_VIP2_MU
LT_PORTB_SRC0
INT_MASK_VIP2_MU
LT_PORTA_SRC15
INT_MASK_VIP2_MU
LT_PORTA_SRC14
INT_MASK_VIP2_MU
LT_PORTA_SRC13
INT_MASK_VIP2_MU
LT_PORTA_SRC12
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
23
22
21
20
19
18
17
16
INT_MASK_VIP2_MU
LT_PORTA_SRC11
INT_MASK_VIP2_MU
LT_PORTA_SRC10
INT_MASK_VIP2_MU
LT_PORTA_SRC9
INT_MASK_VIP2_MU
LT_PORTA_SRC8
INT_MASK_VIP2_MU
LT_PORTA_SRC7
INT_MASK_VIP2_MU
LT_PORTA_SRC6
INT_MASK_VIP2_MU
LT_PORTA_SRC5
INT_MASK_VIP2_MU
LT_PORTA_SRC4
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
15
14
13
12
11
10
9
8
INT_MASK_VIP2_MU
LT_PORTA_SRC3
INT_MASK_VIP2_MU
LT_PORTA_SRC2
INT_MASK_VIP2_MU
LT_PORTA_SRC1
INT_MASK_VIP2_MU
LT_PORTA_SRC0
INT_MASK_VIP1_PO
RTB_RGB
INT_MASK_VIP1_PO
RTA_RGB
INT_MASK_VIP1_PO
RTB_CHROMA
INT_MASK_VIP1_PO
RTB_LUMA
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
7
6
5
4
3
2
1
0
INT_MASK_VIP1_PO
RTA_CHROMA
INT_MASK_VIP1_PO
RTA_LUMA
INT_MASK_VIP1_MU
LT_ANCB_SRC15
INT_MASK_VIP1_MU
LT_ANCB_SRC14
INT_MASK_VIP1_MU
LT_ANCB_SRC13
INT_MASK_VIP1_MU
LT_ANCB_SRC12
INT_MASK_VIP1_MU
LT_ANCB_SRC11
INT_MASK_VIP1_MU
LT_ANCB_SRC10
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-272. VPDMA_int2_channel3_int_mask Register Field Descriptions
Bit
Field
Type
Reset
Description
31
INT_MASK_VIP2_MULT_
PORTB_SRC3
R/W
0h
The interrupt for Video Input 2 Port B Channel 3 should generate an
interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to
trigger the interrupt signal.
30
INT_MASK_VIP2_MULT_
PORTB_SRC2
R/W
0h
The interrupt for Video Input 2 Port B Channel 2 should generate an
interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to
trigger the interrupt signal.
29
INT_MASK_VIP2_MULT_
PORTB_SRC1
R/W
0h
The interrupt for Video Input 2 Port B Channel 1 should generate an
interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to
trigger the interrupt signal.
28
INT_MASK_VIP2_MULT_
PORTB_SRC0
R/W
0h
The interrupt for Video Input 2 Port B Channel 0 should generate an
interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to
trigger the interrupt signal.
27
INT_MASK_VIP2_MULT_
PORTA_SRC15
R/W
0h
The interrupt for Video Input 2 Port A Channel 15 should generate
an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event
to trigger the interrupt signal.
26
INT_MASK_VIP2_MULT_
PORTA_SRC14
R/W
0h
The interrupt for Video Input 2 Port A Channel 14 should generate
an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event
to trigger the interrupt signal.
25
INT_MASK_VIP2_MULT_
PORTA_SRC13
R/W
0h
The interrupt for Video Input 2 Port A Channel 13 should generate
an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event
to trigger the interrupt signal.
24
INT_MASK_VIP2_MULT_
PORTA_SRC12
R/W
0h
The interrupt for Video Input 2 Port A Channel 12 should generate
an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event
to trigger the interrupt signal.
23
INT_MASK_VIP2_MULT_
PORTA_SRC11
R/W
0h
The interrupt for Video Input 2 Port A Channel 11 should generate
an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event
to trigger the interrupt signal.
22
INT_MASK_VIP2_MULT_
PORTA_SRC10
R/W
0h
The interrupt for Video Input 2 Port A Channel 10 should generate
an interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event
to trigger the interrupt signal.
21
INT_MASK_VIP2_MULT_
PORTA_SRC9
R/W
0h
The interrupt for Video Input 2 Port A Channel 9 should generate an
interrupt on interrupt vpdma_int2. Write a 1 for the interrupt event to
trigger the interrupt signal.
