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DEM-DAI1802 Schematics

2-6

Figure 2–5. DEM-DAI1802 A/D Converter Section Schematic Diagram

VDD

C066
0.1uF

U052 PCM1802

C065
10uF/16V

VINL

VINR

VREF1

VREF2

VCC

AGND

PDWN

BYPAS

FSYNC

LRCK

MODE1

MODE0

FMT1

FMT0

TEST

SCKI

VDD

DGND

DOUT

BCK

VINR

VINL

VCC

SCLK

DATA

LRCK

FSYNC

JP052
FFC–12BMEP1

BCK

GND

M/S

SW051

DSS107

C061

10uF/16V

C062
0.1uF

C063

4.7uF/16V

C064

0.1uF

Figure 2–6. DEM-DAI1802 Regulator and Connector Schematic Diagram

VDD

C056

10uF

/16V

C054

100uF

/16V

C053

100uF

/16V

C051

0.1uF

C052

100uF

/16V

GND

OUT

C055

0.1uF

U051

REG1117–3.3

CN057

CN056 B2P–VH

VCC

CN055

Banana

Jack

(Black)

CN053

Banana

Jack

(Blue)

CN054

Banana

Jack

(Red)

CN052

Banana

Jack

(Gray)

CN051

Banana

Jack

(Orange)

AVCC+

AVCC–

Summary of Contents for DEM-DAI1802

Page 1: ... March 2002 DAV Digital Audio Imaging Japan DAL User s Guide SLEU017 ...

Page 2: ...nt that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or end...

Page 3: ... handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR A...

Page 4: ...ere is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 55 C The EVM is designed to operate properly with certain components above 55 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors p...

Page 5: ...02 Single Ended Analog Input 24 Bit 96 kHz Stereo A D Converter Literature No SLES023 FCC Warning This equipment is intended for use in a laboratory test environment only It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protectio...

Page 6: ...vi ...

Page 7: ...2 Schematics 2 5 Figures 1 1 DEM DAI1802 Block Diagram 1 2 1 2 Digital Signal I F to PCM1802 JP052 1 4 2 1 DEM DAI1802 Silkscreen 2 2 2 2 DEM DAI1802 Top View 2 3 2 3 DEM DAI1802 Bottom View 2 4 2 4 DEM DAI1802 Analog Section Schematic Diagram 2 5 2 5 DEM DAI1802 A D Converter Section Schematic Diagram 2 6 2 6 DEM DAI1802 Regulator and Connector Schematic Diagram 2 6 2 7 DEM DAI1802 Digital Sectio...

Page 8: ...versampling Rate Selection JP002 004 052 and SW002 051 1 3 1 5 System Clock Dividing Ratio for MCK 128 fS CS8404 JP001 1 3 1 6 Bit Clock Dividing Ratio JP002 1 3 1 7 LR Clock Dividing Ratio JP004 1 3 1 8 Data Format Selection JP003 and SW051 1 4 1 9 System Clock Source Selection JP005 Internal Clock X001 24 576 MHz External Clock Input CN001 1 4 1 10 Manual Reset SW003 1 4 1 11 S PDIF Transmitter ...

Page 9: ... with digital audio transmitter mode controls switch onboard oscillator 6 dB amplifier and LPF The DEM DAI1802 operates from 5 V and 15 V analog power supplies with a 1 V RMS or 2 V RMS unbalanced analog signal input Topic Page 1 1 Block Diagram 1 2 1 2 DEM DAI1802 Basic Connection and Operation 1 2 Chapter 1 ...

Page 10: ...GND on connectors CN051 CN055 The 15 V supplies are required only for 2 V RMS input Connect the S PDIF output to CN003 COAX or U001 OPT Ensure the presence of a system clock supplied from the onboard oscillator or external input clock connector CN001 through switch jumper to PCM1802 Set the data format using SW001 JP003 and SW051 Select the master or slave mode using SW002 SW051 JP002 JP004 and JP...

Page 11: ...e Table 1 6 Select 128 256 or 512 See Table 1 7 Install SLAVE jumper pin Table 1 5 System Clock Dividing Ratio for MCK 128 fS CS8404 JP001 Dividing Ratio Jumper Pin Position MCK Value 24 576 MHz oscillator default 1 1 1 1 2 2 12 288 MHz 128 fS for fS 96 kHz 1 4 4 6 144 MHz 128 fS for fS 48 kHz Table 1 6 Bit Clock Dividing Ratio JP002 Dividing Ratio Jumper Pin Position BCK Value 24 576 MHz oscillat...

Page 12: ...tion JP005 Internal Clock X001 24 576 MHz External Clock Input CN001 Clock Source Jumper Pin Position Internal INT External EXT Table 1 10 Manual Reset SW003 Reset switch for CS8404 Figure 1 2 Digital Signal I F to PCM1802 JP052 The digital signals generated by the internal oscillator divider and PCM1802 are input to this jumper For each shorted pin the corresponding digital signal is input to the...

Page 13: ...14 Category code 2 of 7 1 1 Not indicated default none 1 1 0000 0000 General 1 0 No emphasis 1 0 0100 0000 PCM encoder decoder 0 1 50 15Us 0 1 1000 0000 CD 0 0 CCITT J 17 0 0 1100 0000 DAT C6 C7 C6 C7 Sample frequency C3 C3 C4 C5 Emphasis 1 of 3 1 1 Not indicated default 48 kHz 1 000 None 1 0 48 kHz 0 100 50 15Us 0 1 44 1 kHz C2 C2 Copy copyright 0 0 32 kHz 1 0 Copy inhibited copyright asserted C1...

Page 14: ...1 6 ...

Page 15: ...cuit Board Schematics and Printed Circuit Board This chapter presents the DEM DAI1802 printed circuit board and the DEM DAI1802 schematics Topic Page 2 1 DEM DAI1802 Printed Circuit Board 2 2 2 2 DEM DAI1802 Schematics 2 5 Chapter 2 ...

Page 16: ...DEM DAI1802 Printed Circuit Board 2 2 2 1 DEM DAI1802 Printed Circuit Board Figure 2 1 DEM DAI1802 Silkscreen ...

Page 17: ...DEM DAI1802 Printed Circuit Board 2 3 Schematics and Printed Circuit Board Figure 2 2 DEM DAI1802 Top VIew ...

Page 18: ...DEM DAI1802 Printed Circuit Board 2 4 Figure 2 3 DEM DAI1802 Bottom View ...

Page 19: ...5 7 8 R110 4 7k C108 100pF JP102 FFC 4BMEP1 AVCC C114 10uF 16V AVCC R104 3 3k C104 1800pF U102 OPA2134PA 1 2 2 3 1 R106 1 2k C106 330pF 4 R102 2 4k CN104 RCA pj C102 10uF 16V R107 4 7k CN101 RCA pj C109 10uF 16V C111 10uF 16V VINL U101 OPA2134PA 2 2 6 5 7 8 R109 4 7k C107 100pF JP101 FFC 4BMEP1 AVCC C113 10uF 16V AVCC R103 3 3k C103 1800pF U101 OPA2134PA 1 2 2 3 1 R105 1 2k C105 330pF 4 R101 2 4k ...

Page 20: ...BCK VINR VINL VCC SCLK DATA LRCK FSYNC JP052 FFC 12BMEP1 BCK GND M S 1 2 3 4 5 6 SW051 DSS107 7 C061 10uF 16V C062 0 1uF C063 4 7uF 16V C064 0 1uF Figure 2 6 DEM DAI1802 Regulator and Connector Schematic Diagram VDD C056 10uF 16V C054 100uF 16V C053 100uF 16V C051 0 1uF C052 100uF 16V 2 1 3 GND IN OUT C055 0 1uF U051 REG1117 3 3 CN057 2 CN056 B2P VH 1 VCC CN055 Banana Jack Black CN053 Banana Jack ...

Page 21: ...6MHz C008 0 1uF U006 74HC245 CN001 BNC R PC4 R002 470 D001 SW003 FP1F 2M C009 10uF 16V R001 47k SW004 DSS108 RA001 47k x8 U004 74VHC14 C006 0 1uF GND GND SCLK DATA BCK LRCK FSYNC SW002 FT2D 2M SLAVE H MASTER L Master Slave Select R007 374 TR001 DA 02 C013 0 1uF JP001 FFC 6B MEP1 5 4 1 6 2 3 GND C01 5 18pF C014 18pF R00 8 1M U007 74HCU04 C7 C3 C7 C3 PRO C1 FC0 C6 C2 MCK SCK FSYNC SDATA V C SBF U C9...

Page 22: ...2 8 ...

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