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D

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B

A

ti

6730 SOUTH TUCSON BLVD., TUCSON, AZ 85706 USA

TITLE

SHEET

OF

FILE

SIZE

DATE

REV

DRAWN BY

ENGINEER

REVISION HISTORY

REV

ENGINEERING CHANGE NUMBER

APPROVED

B

DATA ACQUISITION PRODUCTS

HIGH-PERFORMANCE ANALOG DIVISION

SEMICONDUCTOR GROUP

DOCUMENT CONTROL NO.

DAC8555EVM

A

11-Oct-2006

J. PARGUIAN

R. BENJAMIN

6486604

1

1

C:\USERDATA\Projects\DAC8555\DAC8555EVM.ddb

+5VA

SCLK

VSS

2

3

6

4

7

1

5

U2

OPA627AU

VCC

VCC

EXTERNAL
REFERENCE

1

2

3

R15

100K

1

2

3

R10 20K

VCC

VDD

VDD

VrefH

ENABLE

VSS

+REFin

+REFin

SDI

SCLK

SDI

VDD

-REFin

OUT_A

OUT_B

OUT_C

OUT_D

2

3

1

8

4

U4A
OPA2132UA

5

6

7

U4B

OPA2227UA

-REFin

VrefH

VrefH

VCC

U2_+IN

U2_-IN

U2_OUT

VrefL

VrefL

VCC = +15V Analog

VDD = +2.7V to +5.0V Digital

VSS = 0V to -15V Analog

1

2

3

J1

1

2

3

J5

+5VA

NOTE:  Voltage range of -REFin input should not exceed
 0 - VrefH.

VCC

VSS

+5VA

-5VA

VDD

+3.3VD +1.8VD

+3.3VA

LDAC

SYNC

LDAC

ENABLE

RSTSEL

RST

RSTSEL

RST

SYNC

+3.3VA

AVDD

-VA

2

-5VA

4

AGND

6

VD1

8

+5VD

10

+VA

1

+5VA

3

DGND

5

+1.8VD

7

+3.3VD

9

J3A

DAUGHTER-POWER

A0(+)

2

A1(+)

4

A2(+)

6

A3(+)

8

A4

10

A5

12

A6

14

A7

16

REF-

18

REF+

20

A0(-)

1

A1(-)

3

A2(-)

5

A3(-)

7

AGND

9

AGND

11

AGND

13

VCOM

15

AGND

17

AGND

19

J4A

OUTPUT HEADER

GPIO0

2

DGND

4

GPIO1

6

GPIO2

8

DGND

10

GPIO3

12

GPIO4

14

SCL

16

DGND

18

SDA

20

CNTL

1

CLKX

3

CLKR

5

FSX

7

FSR

9

DX

11

DR

13

INT

15

TOUT

17

GPIO5

19

J2A

DAUGHTER-SERIAL

R1
10K

R2
10K

R3
10K

R4
10K

R5
NI

R6
NI

C5
0.1uF

C2
10uF

1

2

3

JMP7

C7
0.1uF

C3
10uF

R11

0

R12

0

1

2

JMP2

1

2

JMP1

1

2

JMP4

1

2

JMP3

VIN

2

VOUT

6

TRIM

5

GN

D

4

TEMP

3

U3

REF02AU

C1
10uF

C4
0.1uF

TP1

REF OUT

R13

0

R16
20k

C6

0.1uF

1
2
3

JMP8

1

2

3

JMP9

TP4

AGND

TP3

TP2

TP5
+Vin
TP6
-Vin

R18
NI

R21

NI

R19 NI

R20 NI

R22

NI

R23

NI

R17

NI

C9

NI

C8

NI

R14

0

R7
10K

R9

10K

R8

10K

R24

100

C11

1uF

C10

1uF

C12

1nF

1

2

JMP5

1

2

JMP6

1

2

3

JMP10

1

2

3

JMP15
OPA IN

1

2

3

JMP16
OPA OUT

1
2
3

JMP11

OUT A

1
2
3

JMP12

OUT B

1
2
3

JMP13

OUT C

1
2
3

JMP14

OUT D

J4A (TOP) = SAM_TSM-110-01-L-DV-P
J4B (BOTTOM) = SAM_SSW-110-22-F-D-VS-K

J2A (TOP) = SAM_TSM-110-01-L-DV-P
J2B (BOTTOM) = SAM_SSW-110-22-F-D-VS-K

J3A (TOP) = SAM_TSM-105-01-L-DV-P
J3B (BOTTOM) = SAM_SSW-105-22-F-D-VS-K

VoutB

2

IO_V/DVDD

12

LDAC

16

RSTSEL

14

GND

6

VrefH

3

VrefL

5

VoutA

1

ENABLE

15

RST

13

VoutD

8

Din

11

SCLK

10

SYNC

9

AVDD

4

VoutC

7

U1

DAC8555IPW

Summary of Contents for DAC8555EVM

Page 1: ...For a more detailed description of the DAC8555 see the product data sheet available from the Texas Instruments web site at http www ti com Additional support documents are listed in the section of th...

Page 2: ...creen Image 9 8 DAC8555EVM Drill Drawing 10 9 INL and DNL Characterization Graph of DAC A 11 10 INL and DNL Characterization Graph of DAC B 12 11 INL and DNL Characterization Graph of DAC C 13 12 INL...

Page 3: ...7 This configuration allows the DAC8555 analog section to operate from either supply power while the I O and digital section are powered by 5V VDD The VCC supply source is primarily used to provide th...

Page 4: ...ing a custom cable Additionally there is also an MSP430 based platform HPA449 that uses the MSP430F449 microprocessor to which this EVM can connect and interface as well For more details or informatio...

Page 5: ...P15 JMP16 JMP9 JMP10 DAC Out VSS V H REF TP4 TP3 VCC GND VSS GND VDD 5VA 3 3VA DIN LDAC SCLK SYNC JMP5 JMP6 JMP4 JMP3 JMP8 V H REF TP2 VSS VCC V L REF Output Buffer Module RST RSTSEL RSTSEL EN RST Ove...

Page 6: ...ce the bypass capacitors as close as possible to the device pins and properly separate the analog and digital signals from each other In the layout process carefully consider the placement of the powe...

Page 7: ...i com PCB Design and Performance Figure 2 DAC8555EVM PCB Top Silkscreen Image Figure 3 DAC8555EVM PCB Layer 1 Top Signal Layer SLAU204 December 2006 DAC8555EVM User s Guide 7 Submit Documentation Feed...

Page 8: ...w ti com PCB Design and Performance Figure 4 DAC8555EVM PCB Layer 2 Ground Plane Figure 5 DAC8555EVM PCB Layer 3 Power Plane 8 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedba...

Page 9: ...om PCB Design and Performance Figure 6 DAC8555EVM PCB Layer 4 Bottom Signal Layer Figure 7 DAC8555EVM PCB Bottom Silkscreen Image SLAU204 December 2006 DAC8555EVM User s Guide 9 Submit Documentation F...

Page 10: ...nd a PC running LabVIEW software The EVM board is tested for linearity for all codes between 485 and 64741 The DUT is then allowed to settle for 1ms before the meter is read This process is repeated f...

Page 11: ...www ti com PCB Design and Performance Figure 9 INL and DNL Characterization Graph of DAC A SLAU204 December 2006 DAC8555EVM User s Guide 11 Submit Documentation Feedback...

Page 12: ...www ti com PCB Design and Performance Figure 10 INL and DNL Characterization Graph of DAC B 12 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback...

Page 13: ...www ti com PCB Design and Performance Figure 11 INL and DNL Characterization Graph of DAC C SLAU204 December 2006 DAC8555EVM User s Guide 13 Submit Documentation Feedback...

Page 14: ...www ti com PCB Design and Performance Figure 12 INL and DNL Characterization Graph of DAC D DAC8555EVM User s Guide 14 SLAU204 December 2006 Submit Documentation Feedback...

Page 15: ...2 C3 TDK C3216X7R1C106M Multilayer Ceramic Capacitor 10 F 1206 X7R Not 2 C8 C9 TDK Multilayer Ceramic Capacitor 1206 Installed 16 bit Quad Voltage Output Serial Input DAC 11 1 U1 Texas Instruments DAC...

Page 16: ...ed to the noninverting input of the output op amp U2 JMP16 1 2 J4 5 is connected to the output of the op amp U2 The host processor drives the DAC Thus proper DAC operation depends on a successful conf...

Page 17: ...al stability when stacking or plugging into any interface card In addition it provides easy access for monitoring up to eight DAC channels when stacking two EVMs together The DAC8555EVM includes an op...

Page 18: ...om the gain resistor R9 There are two types of configurations that will yield an output gain of 2 depending on the setup of jumpers JMP5 and JMP6 These configurations allow the user to choose whether...

Page 19: ...fering U4A while the other half is unused This unused op amp U4B is left for whatever op amp circuit application the user desires to implement The 1206 footprint for the resistors and capacitors surro...

Page 20: ...ain of 2 5V analog supply is selected for AVDD JMP7 3 3V analog supply is selected for AVDD Routes the adjustable buffered onboard 5V reference to the VREFH input of the DAC8555 JMP8 Routes the user s...

Page 21: ...VOUTB to J4 4 JMP12 Routes VOUTB to J4 12 Routes VOUTC to J4 6 JMP13 Routes VOUTC to J4 14 Routes VOUTD to J4 8 JMP14 Routes VOUTD to J4 16 Routes J4 1 to U2 noninverting input JMP15 Routes J4 3 to U...

Page 22: ...www ti com 4 Schematic Schematic 22 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback...

Page 23: ...4 A2 6 A3 8 A4 10 A5 12 A6 14 A7 16 REF 18 REF 20 A0 1 A1 3 A2 5 A3 7 AGND 9 AGND 11 AGND 13 VCOM 15 AGND 17 AGND 19 J4A OUTPUT HEADER GPIO0 2 DGND 4 GPIO1 6 GPIO2 8 DGND 10 GPIO3 12 GPIO4 14 SCL 16 D...

Page 24: ...uction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER P...

Page 25: ...iness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product wou...

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