background image

www.ti.com

3.4.3

Capacitive Load Drive

3.5

Optional Signal Conditioning Op-Amp (U4B)

3.6

Jumper Settings

EVM Operation

It may be required to drive a wide range of capacitive loads. However, under certain conditions, all op
amps may become unstable, depending on the op amp configuration, gain, and load value. These factors
are just few of the issues that can affect op amp stability and should be considered during implementation.

In unity gain configuration, the OPA627 op amp (U2) performs very well with very large capacitive loads.
Increasing the gain enhances amplifier ability to drive even more capacitance, and adding a load resistor
even improves the capacitive load drive capability.

Table 6

shows the jumper setting configuration for a capacitive load drive.

Table 6. Capacitive Load Drive Output Jumper Settings

Jumper Setting

Reference

Unipolar

Bipolar

Function

JMP5

Open

Open

V

REF

H is disconnected from the inverting input of the output op amp U2.

Supplies power, V

SS

, to the negative rail of op amp U2 for bipolar mode, or ties it to AGND

JMP10

2-3

1-2

for unipolar mode.

Capacitive load drive output of DAC is routed to pin 2 of JMP6 and may be used as the

JMP6

Open

Open

output terminal.

One half of the OPA2132 dual package op amp (U4) is used for reference buffering (U4A), while the other
half is unused. This unused op amp (U4B) is left for whatever op amp circuit application the user desires
to implement. The 1206 footprint for the resistors and capacitors surrounding the U4B op amp are not
populated and are made available for easy configuration. Test points TP5 and TP6 are not installed, so it
is up to the user on how to connect the (

±

) input signals to this op amp. No test point has been made

available for the output because of space restrictions, but a wire can be soldered to the output of the op
amp via an unused component pad that connects to it. The op amp circuit can be configured by populating
the corresponding components to those that match the circuit design while leaving all other unused
component footprints unpopulated.

Table 7

shows the function of each specific jumper setting of the EVM.

Table 7. Jumper Settings and Functions

Reference

Jumper Setting

(1)

Function

ENABLE pin is set high through pull-up resistor R1. ENABLE can be driven by GPIO2,
J2-8.

JMP1

ENABLE pin is set low and DAC is enabled.

LDAC pin is set high through pull-up resistor R2. LDAC can be driven by GPIO0, J2-2.

JMP2

LDAC pin is set low and DAC update is accomplished via software.

RSTSEL pin is set high through pull-up resistor R3. RSTSEL can be driven by GPIO4,
J2-14.

JMP3

RSTSEL pin is set low.

(1)

Indicates the corresponding pins that are shorted or closed.

SLAU204 – December 2006

DAC8555EVM User's Guide

19

Submit Documentation Feedback

Summary of Contents for DAC8555EVM

Page 1: ...For a more detailed description of the DAC8555 see the product data sheet available from the Texas Instruments web site at http www ti com Additional support documents are listed in the section of th...

Page 2: ...creen Image 9 8 DAC8555EVM Drill Drawing 10 9 INL and DNL Characterization Graph of DAC A 11 10 INL and DNL Characterization Graph of DAC B 12 11 INL and DNL Characterization Graph of DAC C 13 12 INL...

Page 3: ...7 This configuration allows the DAC8555 analog section to operate from either supply power while the I O and digital section are powered by 5V VDD The VCC supply source is primarily used to provide th...

Page 4: ...ing a custom cable Additionally there is also an MSP430 based platform HPA449 that uses the MSP430F449 microprocessor to which this EVM can connect and interface as well For more details or informatio...

Page 5: ...P15 JMP16 JMP9 JMP10 DAC Out VSS V H REF TP4 TP3 VCC GND VSS GND VDD 5VA 3 3VA DIN LDAC SCLK SYNC JMP5 JMP6 JMP4 JMP3 JMP8 V H REF TP2 VSS VCC V L REF Output Buffer Module RST RSTSEL RSTSEL EN RST Ove...

Page 6: ...ce the bypass capacitors as close as possible to the device pins and properly separate the analog and digital signals from each other In the layout process carefully consider the placement of the powe...

Page 7: ...i com PCB Design and Performance Figure 2 DAC8555EVM PCB Top Silkscreen Image Figure 3 DAC8555EVM PCB Layer 1 Top Signal Layer SLAU204 December 2006 DAC8555EVM User s Guide 7 Submit Documentation Feed...

Page 8: ...w ti com PCB Design and Performance Figure 4 DAC8555EVM PCB Layer 2 Ground Plane Figure 5 DAC8555EVM PCB Layer 3 Power Plane 8 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedba...

Page 9: ...om PCB Design and Performance Figure 6 DAC8555EVM PCB Layer 4 Bottom Signal Layer Figure 7 DAC8555EVM PCB Bottom Silkscreen Image SLAU204 December 2006 DAC8555EVM User s Guide 9 Submit Documentation F...

Page 10: ...nd a PC running LabVIEW software The EVM board is tested for linearity for all codes between 485 and 64741 The DUT is then allowed to settle for 1ms before the meter is read This process is repeated f...

Page 11: ...www ti com PCB Design and Performance Figure 9 INL and DNL Characterization Graph of DAC A SLAU204 December 2006 DAC8555EVM User s Guide 11 Submit Documentation Feedback...

Page 12: ...www ti com PCB Design and Performance Figure 10 INL and DNL Characterization Graph of DAC B 12 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback...

Page 13: ...www ti com PCB Design and Performance Figure 11 INL and DNL Characterization Graph of DAC C SLAU204 December 2006 DAC8555EVM User s Guide 13 Submit Documentation Feedback...

Page 14: ...www ti com PCB Design and Performance Figure 12 INL and DNL Characterization Graph of DAC D DAC8555EVM User s Guide 14 SLAU204 December 2006 Submit Documentation Feedback...

Page 15: ...2 C3 TDK C3216X7R1C106M Multilayer Ceramic Capacitor 10 F 1206 X7R Not 2 C8 C9 TDK Multilayer Ceramic Capacitor 1206 Installed 16 bit Quad Voltage Output Serial Input DAC 11 1 U1 Texas Instruments DAC...

Page 16: ...ed to the noninverting input of the output op amp U2 JMP16 1 2 J4 5 is connected to the output of the op amp U2 The host processor drives the DAC Thus proper DAC operation depends on a successful conf...

Page 17: ...al stability when stacking or plugging into any interface card In addition it provides easy access for monitoring up to eight DAC channels when stacking two EVMs together The DAC8555EVM includes an op...

Page 18: ...om the gain resistor R9 There are two types of configurations that will yield an output gain of 2 depending on the setup of jumpers JMP5 and JMP6 These configurations allow the user to choose whether...

Page 19: ...fering U4A while the other half is unused This unused op amp U4B is left for whatever op amp circuit application the user desires to implement The 1206 footprint for the resistors and capacitors surro...

Page 20: ...ain of 2 5V analog supply is selected for AVDD JMP7 3 3V analog supply is selected for AVDD Routes the adjustable buffered onboard 5V reference to the VREFH input of the DAC8555 JMP8 Routes the user s...

Page 21: ...VOUTB to J4 4 JMP12 Routes VOUTB to J4 12 Routes VOUTC to J4 6 JMP13 Routes VOUTC to J4 14 Routes VOUTD to J4 8 JMP14 Routes VOUTD to J4 16 Routes J4 1 to U2 noninverting input JMP15 Routes J4 3 to U...

Page 22: ...www ti com 4 Schematic Schematic 22 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback...

Page 23: ...4 A2 6 A3 8 A4 10 A5 12 A6 14 A7 16 REF 18 REF 20 A0 1 A1 3 A2 5 A3 7 AGND 9 AGND 11 AGND 13 VCOM 15 AGND 17 AGND 19 J4A OUTPUT HEADER GPIO0 2 DGND 4 GPIO1 6 GPIO2 8 DGND 10 GPIO3 12 GPIO4 14 SCL 16 D...

Page 24: ...uction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER P...

Page 25: ...iness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product wou...

Reviews: