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FCC Warning

This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY 
and is not considered by TI to be a finished end-product fit for general customer use. It generates, uses, and
can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15
of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this
equipment in other environments may cause interference with radio communications, in which case the user at his own expense
will be required to take whatever measures may be required to correct this interference.

EVALUATION BOARD/KIT IMPORTANT NOTICE

Texas Instruments (TI) provides the enclosed product(s) under the following conditions:

This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY 
and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the
product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are
not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations,
including product safety and environmental measures typically found in end products that incorporate such semiconductor
components or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding
electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the
technical requirements of these directives or other related directives.

Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30
days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY
SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING
ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all
claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to
take any and all appropriate precautions with regard to electrostatic discharge.

EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER
FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.

TI assumes no liability for applications assistance, customer product design, software performance, or infringement of
patents or services described herein.

Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the
product. This notice contains important safety information about temperatures and voltages. For additional information on TI’s
environmental and/or safety programs, please contact the TI application engineer or visit

www.ti.com/esh

.

No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used.

EVM WARNINGS AND RESTRICTIONS

It is important to operate this EVM within the input voltage range of–15.75V to +15.75V and the output voltage range of –15V to
+15V.

Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.

Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative.

During normal operation, some circuit components may have case temperatures greater than 60

°

C. The EVM is designed to

operate properly with certain components above 60

°

C as long as the input and output ranges are maintained. These components

include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of
devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near
these devices during operation, please be aware that these devices may be very warm to the touch.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright© 2006, Texas Instruments Incorporated

Summary of Contents for DAC8555EVM

Page 1: ...For a more detailed description of the DAC8555 see the product data sheet available from the Texas Instruments web site at http www ti com Additional support documents are listed in the section of th...

Page 2: ...creen Image 9 8 DAC8555EVM Drill Drawing 10 9 INL and DNL Characterization Graph of DAC A 11 10 INL and DNL Characterization Graph of DAC B 12 11 INL and DNL Characterization Graph of DAC C 13 12 INL...

Page 3: ...7 This configuration allows the DAC8555 analog section to operate from either supply power while the I O and digital section are powered by 5V VDD The VCC supply source is primarily used to provide th...

Page 4: ...ing a custom cable Additionally there is also an MSP430 based platform HPA449 that uses the MSP430F449 microprocessor to which this EVM can connect and interface as well For more details or informatio...

Page 5: ...P15 JMP16 JMP9 JMP10 DAC Out VSS V H REF TP4 TP3 VCC GND VSS GND VDD 5VA 3 3VA DIN LDAC SCLK SYNC JMP5 JMP6 JMP4 JMP3 JMP8 V H REF TP2 VSS VCC V L REF Output Buffer Module RST RSTSEL RSTSEL EN RST Ove...

Page 6: ...ce the bypass capacitors as close as possible to the device pins and properly separate the analog and digital signals from each other In the layout process carefully consider the placement of the powe...

Page 7: ...i com PCB Design and Performance Figure 2 DAC8555EVM PCB Top Silkscreen Image Figure 3 DAC8555EVM PCB Layer 1 Top Signal Layer SLAU204 December 2006 DAC8555EVM User s Guide 7 Submit Documentation Feed...

Page 8: ...w ti com PCB Design and Performance Figure 4 DAC8555EVM PCB Layer 2 Ground Plane Figure 5 DAC8555EVM PCB Layer 3 Power Plane 8 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedba...

Page 9: ...om PCB Design and Performance Figure 6 DAC8555EVM PCB Layer 4 Bottom Signal Layer Figure 7 DAC8555EVM PCB Bottom Silkscreen Image SLAU204 December 2006 DAC8555EVM User s Guide 9 Submit Documentation F...

Page 10: ...nd a PC running LabVIEW software The EVM board is tested for linearity for all codes between 485 and 64741 The DUT is then allowed to settle for 1ms before the meter is read This process is repeated f...

Page 11: ...www ti com PCB Design and Performance Figure 9 INL and DNL Characterization Graph of DAC A SLAU204 December 2006 DAC8555EVM User s Guide 11 Submit Documentation Feedback...

Page 12: ...www ti com PCB Design and Performance Figure 10 INL and DNL Characterization Graph of DAC B 12 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback...

Page 13: ...www ti com PCB Design and Performance Figure 11 INL and DNL Characterization Graph of DAC C SLAU204 December 2006 DAC8555EVM User s Guide 13 Submit Documentation Feedback...

Page 14: ...www ti com PCB Design and Performance Figure 12 INL and DNL Characterization Graph of DAC D DAC8555EVM User s Guide 14 SLAU204 December 2006 Submit Documentation Feedback...

Page 15: ...2 C3 TDK C3216X7R1C106M Multilayer Ceramic Capacitor 10 F 1206 X7R Not 2 C8 C9 TDK Multilayer Ceramic Capacitor 1206 Installed 16 bit Quad Voltage Output Serial Input DAC 11 1 U1 Texas Instruments DAC...

Page 16: ...ed to the noninverting input of the output op amp U2 JMP16 1 2 J4 5 is connected to the output of the op amp U2 The host processor drives the DAC Thus proper DAC operation depends on a successful conf...

Page 17: ...al stability when stacking or plugging into any interface card In addition it provides easy access for monitoring up to eight DAC channels when stacking two EVMs together The DAC8555EVM includes an op...

Page 18: ...om the gain resistor R9 There are two types of configurations that will yield an output gain of 2 depending on the setup of jumpers JMP5 and JMP6 These configurations allow the user to choose whether...

Page 19: ...fering U4A while the other half is unused This unused op amp U4B is left for whatever op amp circuit application the user desires to implement The 1206 footprint for the resistors and capacitors surro...

Page 20: ...ain of 2 5V analog supply is selected for AVDD JMP7 3 3V analog supply is selected for AVDD Routes the adjustable buffered onboard 5V reference to the VREFH input of the DAC8555 JMP8 Routes the user s...

Page 21: ...VOUTB to J4 4 JMP12 Routes VOUTB to J4 12 Routes VOUTC to J4 6 JMP13 Routes VOUTC to J4 14 Routes VOUTD to J4 8 JMP14 Routes VOUTD to J4 16 Routes J4 1 to U2 noninverting input JMP15 Routes J4 3 to U...

Page 22: ...www ti com 4 Schematic Schematic 22 DAC8555EVM User s Guide SLAU204 December 2006 Submit Documentation Feedback...

Page 23: ...4 A2 6 A3 8 A4 10 A5 12 A6 14 A7 16 REF 18 REF 20 A0 1 A1 3 A2 5 A3 7 AGND 9 AGND 11 AGND 13 VCOM 15 AGND 17 AGND 19 J4A OUTPUT HEADER GPIO0 2 DGND 4 GPIO1 6 GPIO2 8 DGND 10 GPIO3 12 GPIO4 14 SCL 16 D...

Page 24: ...uction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER P...

Page 25: ...iness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product wou...

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