Texas Instruments DAC5686 EVM, User Manual

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4.3 Output Data
4.3.1 Transformer-Coupled Signal Output
Circuit Description
Table 2. Input Connector J13 (Data A Bus) (continued)
Pin Description Pin Description
11 CMOS data bit 10 28 GND
12 GND 29 CMOS data bit 1
13 CMOS data bit 9 30 GND
14 GND 31 CMOS data bit 0 (LSB)
15 CMOS data bit 8 32 GND
16 GND 33
17 CMOS data bit 7 34 GND
Table 3. Input Connector J14 (Data B Bus)
Pin Description Pin Description
1 CMOS data bit 0 (LSB) 18 GND
2 GND 19 CMOS data bit 9
3 CMOS data bit 1 20 GND
4 GND 21 CMOS data bit 10
5 CMOS data bit 2 22 GND
6 GND 23 CMOS data bit 11
7 CMOS data bit 3 24 GND
8 GND 25 CMOS data bit 12
9 CMOS data bit 4 26 GND
10 GND 27 CMOS data bit 13
11 CMOS data bit 5 28 GND
12 GND 29 CMOS data bit 14
13 CMOS data bit 6 30 GND
14 GND 31 CMOS data bit 15 (MSB)
15 CMOS data bit 7 32 GND
16 GND 33
17 CMOS data bit 8 34 GND
The DAC5686 EVM can be configured to drive a doubly terminated 50-W cable or provide unbuffered
differential outputs.
The factory-set configuration of the demonstration board provides the user with single-ended output
signals at SMA connectors J5 and J19. The DAC5686 outputs are configured to drive a doubly terminated
50-
Ω
cable using a 4:1 impedance ratio transformer with the center tap of the transformers connected to
+3.3 VA as shown in Table 4 . When using a 1:1 impedance ratio transformer, configure the EVM as
shown in Table 4 . The common mode input voltage of T1 and T2 can be adjusted by using the resistor
divider networks.
Table 4. Transformer Output Configuration
Configuration Components Installed
(1)
Components Not Installed
1:1 Impedance ratio transformer R5 (49.9), R10 (49.9), R19 (49.9), R20 (49.9), R21–R23, R26, R24, R27–R33
C60, C61, T1(1:1), T2 (1:1)
4:1 Impedance ratio transformer R5, R10, R19, R20, R23, R26, C60, C61, T1, T2 R21, R22, R24, R27-R33
(1)
All component values are per the schematic except where shown in parenthesis.
DAC5686 EVM 22 SLWU006E – December 2004 – Revised March 2007
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