www.ti.com
2.3.2
Configuration Controls
DAC5686 EVM Operational Procedure
•
Full Bypass: When set, all interpolation and NCO functions are bypassed. User can only use
CLK2/CLK2C inputs in this mode.
•
Counter: Uses an input counter ramp as the input data to the DAC. See the DAC5686 data sheet for
more information.
•
2's Comp: When set, input data is interpreted as 2's complement. When cleared, input data is
interpreted as offset binary.
•
Sync_Phstr: Enables the PHSTR input as a sync input to the clock dividers in external single clock
mode. For example, in external single clock mode (PLLVDD = 0), with 16x interpolation, the
CLK2/CLK2C signal is divided by 16 and output on the PLLLOCK pin. If this bit is set, a rising edge on
the PHSTR pin will be sampled by the CLK2/CLK2C clock, and used to restart the divide by 16 circuit.
•
Dither: Enables dithering in the PLL.
•
Rev B Bus: When cleared, DB input data MSB to LSB order is DB(15)= MSB and DB(0)=LSB. When
set, DB input data MSB to LSB order is reversed, DB(15) = LSB and DB(0) = MSB.
•
qflag: Sets qflag bit. When set, the QFLAG input pin operates as a B sample indicator when
interleaved data is enabled. When cleared, the TXENABLE rising determines the A/B timing
relationship.
•
Rev. Spect: When asserted the sin term is negated before being used in mixing. This gives the
reverse spectrum in single sideband mode.
•
Interleave: When set, interleaved input data mode is enabled; both A and B data streams are input at
the DA(15:0) input pins. The TXENABLE or QFLAG pin is used to identify the I/Q sequence depending
on the value the "Qflag Interleave" bit (see the following)
•
Inverse Sinc: Enables inverse sinc correction filter.
•
Dual Clk: Only used when the PLL is disabled. When set, two differential clocks are used to input the
data to the chip; CLK1/CLK1C is used to latch the input data into the chip, and CLK2/CLK2C is used
as the DAC sample clock.
•
NCO: When set, enables NCO in Single Sideband or Quad Mod modes. The NCO is operational up to
350 MHz DAC update clock. When cleared, Single Sideband and Quad Mod modes use a fixed fs/4
mix frequency.
•
Sif: Sets sif_4pin bit. The 4 pin serial interface mode is enabled when on, 3 pin mode when off. The
DAC5686 EVM is configured for a 3 pin serial interface, so setting to a 4 bit serial interface makes
reading registers impossible with the GUI.
•
Single Sideband: When set, the data to DACB is inverted to generate upper side band output.
•
Mode: Used to select the DAC mixer mode.
–
Dual DAC - runs the device in dual DAC mode; no mixing between the A and B datapaths.
–
Quad Mod - runs the device as a quadrature modulator. The DACA circuit is shut off and the output
is on the DACB outputs.
–
Single Sideband - The device generates a hilbert transform pair on the DACA and DACB outputs
suitable for connection to an analog quadrature modulator.
•
PLL Divider: Sets PLL VCO divider to div by 1, 2, 4, or 8. Only valid when the PLL is enabled by
pro3.3 V to PLLVDD (W3 between pins 1 and 2). The VCO works best (low phase noise) when
biased in the 250 to 500 MHz range. If the device is to be run with a DAC update rate below 250 MHz,
set the PLL divider to 2. This allows the user to run the VCO at the 250 to 500 MHz range since the
output is divided by 2.
•
Interpolation: Sets FIR Interpolation factor: {×2, ×4, ×8, ×16}.
•
Gain Dig/Analog: Sets the gain of the DDS to ensure that the overall gain is less than or equal to 1
(i.e. no clipping). See the DAC5686 data sheet for more information.
•
PLLVCO Boost: Increases the Vtol current of the PLL VCO from nominal to 45% in 15% increments.
DAC5686 EVM
14
SLWU006E – December 2004 – Revised March 2007
