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ti

12500 TI Boulevard.  Dallas, Texas 75243

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21−Mar−2006

DOCUMENTCONTROL #

DAC5686

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Schematic

Figure 10. Schematic - Page 2

SLWU006E – December 2004 – Revised March 2007

DAC5686 EVM

27

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Summary of Contents for DAC5686 EVM

Page 1: ...DAC5686 EVM User s Guide March 2007 Wireless Infrastructure Products SLWU006E...

Page 2: ...2 SLWU006E December 2004 Revised March 2007 Submit Documentation Feedback...

Page 3: ...86 EVM Initial Setup Tests 11 2 3 DAC5686 GUI Register Descriptions 13 3 Physical Description 15 3 1 PCB Layout 15 3 2 Parts List 19 4 Circuit Description 21 4 1 Input Clocks 21 4 2 Input Data 21 4 3...

Page 4: ...ff 12 4 Spectrum with CLK2 320 MHz X4 Interpolation Single Sideband Mode and NCO Frequency 536870912 13 5 Top Layer 1 16 6 Layer 2 Ground Plane 17 7 Layer 3 Power Plane 18 8 Bottom Layer 19 9 Schemati...

Page 5: ...EVM allows for different clock configurations The user can input a single ended differential ECL PECL or TTL CMOS level signal to be used to generate a single ended or differential clock source See Se...

Page 6: ...rough RBIAS resistor R1 The DAC5686 output is enabled sleep mode disabled TXENABLE is set high to enable the DAC5686 device to process data Internal PLL disabled Jumper W3 is installed between pins 2...

Page 7: ...cable to J1 on the EVM and skip steps 2 to 7 2 USB Interface Connect the provided USB to SPI adapter board to the parallel port connector on the EVM and to a spare USB port on the host PC using the s...

Page 8: ...k and select Install from a list or specific location advanced Click Next 5 Select Search for the best driver in these locations and browse for the folder where the DAC5686 program was installed the d...

Page 9: ...ing a Microsoft WHQL certified driver Click on Continue Anyway to continue with the installation If Windows XP is configured to ignore file signature warnings no message will appear 7 Windows should t...

Page 10: ...re is a problem with the communication such as the EVM is not powered on or the parallel port cable is not connected an error message will be displayed instructing the user to correct the problem Once...

Page 11: ...ovide a CLK2 input and disable the internal PLL W3 between pins 2 and 3 Do not provide parallel input data 2 Power up the EVM with 1 8 V DVDD and 3 3 V AVDD 3 Start the DAC5686_SPI software 4 Turn Ful...

Page 12: ...TB In the case of CLK2 500 MHz the output spectrum should be similar to Figure 3 with a tone at 125 MHz This tone is being generated by the DAC5686 Fdac 4 Coarse Mixer as with no input data provided t...

Page 13: ...lation Single Sideband Mode and NCO Frequency 536870912 6 Changing the NCO DDS to 268435456 232 20 320 will now result at an output tone at 20 MHz The following section provides a brief description of...

Page 14: ...differential clocks are used to input the data to the chip CLK1 CLK1C is used to latch the input data into the chip and CLK2 CLK2C is used as the DAC sample clock NCO When set enables NCO in Single S...

Page 15: ...error message will be displayed This chapter describes the physical characteristics and PCB layout of the EVM and lists the components used on the module The EVM is constructed on a 4 layer 6 5 inch...

Page 16: ...www ti com Physical Description Figure 5 Top Layer 1 16 DAC5686 EVM SLWU006E December 2004 Revised March 2007 Submit Documentation Feedback...

Page 17: ...www ti com Physical Description Figure 6 Layer 2 Ground Plane SLWU006E December 2004 Revised March 2007 DAC5686 EVM 17 Submit Documentation Feedback...

Page 18: ...www ti com Physical Description Figure 7 Layer 3 Power Plane 18 DAC5686 EVM SLWU006E December 2004 Revised March 2007 Submit Documentation Feedback...

Page 19: ...ti com 3 2 Parts List Physical Description Figure 8 Bottom Layer Table 1 lists the parts used in constructing the EVM SLWU006E December 2004 Revised March 2007 DAC5686 EVM 19 Submit Documentation Feed...

Page 20: ...F10R0V Panasonic R3 R15 0 resistor 1 16 W 1 2 ERJ 3GEY0R00V Panasonic R23 R26 R24 R27 R33 49 9 resistor 1 16 W 1 3 ERJ 3EKF49R9V Panasonic R12 R13 R39 R40 127 resistor 1 16 W 1 1 ERJ 3EKF1270V Panason...

Page 21: ...the clock source should feature very low jitter Using a clock with a 50 duty cycle gives optimum dynamic performance A 300 mVPP 0 V offset 50 duty cycle external square wave is applied to SMA connect...

Page 22: ...ured to drive a doubly terminated 50 W cable or provide unbuffered differential outputs The factory set configuration of the demonstration board provides the user with single ended output signals at S...

Page 23: ...pins 5 and 6 on header J15 The DAC5686 EVM provides a means of resetting the DAC5686 device Pressing switch S1 or sending J15 pin 29 low provides an active low reset signal to the DAC5686 device The D...

Page 24: ...e output current IOUTFS is defined as follows where VEXTIO is the voltage at pin EXTIO This voltage is 1 2 V typical when using the internally provided bandgap reference voltage source The internal re...

Page 25: ...www ti com 5 Schematic Schematic This chapter contains the DAC5686 EVM schematic diagrams SLWU006E December 2004 Revised March 2007 DAC5686 EVM 25 Submit Documentation Feedback...

Page 26: ...0 Note 1 Note 1 Note 1 Note 1 IOUTB 3 3VA 3 3VA NOTE 1 DO NOT INSTALL 1 2 3 4 5 J2 SMA C25 1uF C26 10uF IOVDD CLK1C CLK1 CLK2 CLK2C SH 3 SH 3 SH 3 SH 3 PHSTR SH 2 SDO SDO SH 4 4 6 3 2 1 T2 T4 1 KK81...

Page 27: ...14 A15 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 J13 34PIN_IDC 1 2 3 4 5 6 7 8 9 10 11 12 13 14...

Page 28: ...1 200 1 2 3 4 5 J3 SMA C19 01uF CLK1 CLK1 CLK1C CLK1 CLK1C R14 200 1 2 3 4 5 J4 SMA C20 01uF CLK2 CLK2 CLK2C CLK2 CLK2C DAC5686 B 3 5 J SETON Y DEWONCK 1 PART NOT INSTALLED NOTES 3 1 4 6 2 T4 TCM4 1W...

Page 29: ...5 12 J1 DB25F RA R34 10K R35 10K R36 10K R37 10K R3 10 SDENB SCLK SDIO C21 1uF 3 3V_SER SDIO SCLK SDENB SH 1 SH 1 SH 1 OE1_ 1 1A1 2 1A2 4 1A3 6 1A4 8 2A1 11 2A2 13 2A3 15 2A4 17 GND 10 2Y4 3 2Y3 5 2Y2...

Page 30: ...VDD FB2 C28 10uF C42 1uF C48 0 01uF C54 47 uF C30 10uF C43 1uF C49 0 01uF FB3 1 8VD VD J8 RED VD C55 47 uF 3 3VPLL FB5 C32 10uF C45 1uF C51 0 01uF C57 47 uF 3 3VCLK FB6 C35 10uF C46 1uF C52 0 01uF C58...

Page 31: ...temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license is granted under any pa...

Page 32: ...iness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product wou...

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