Texas Instruments DAC38RF80EVM, User Manual

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Introduction
3 SLAU671A – October 2016 – Revised March 2017
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DAC38RF8xEVM
Table 1. DAC38RF8xEVM Component Description
Part Description
DAC38RF8x 9 Gsps dual-channel DAC with JESD204B interface
FMC Connector Interface to connect DAC evaluation board to pattern generators (for example, TSW14J56)
LMK04828 JESD204B-compliant clock generator. Used to generate SYSREF and device clock to pattern generator. Also
generates SYSREF and PLL reference clock to DAC38RF8x.
NB7V33M 10 GHz divide by 4 clock divider
TCM3-452X-1+ 2:1 impedance ratio transformer. Used for (1) impedance matching to 50- Ω load, (2) differential to single-ended
conversion, (3) DC biasing of DAC output.
TCM2-43X+ 2:1 impedance ratio transformer. Used to convert CLKTX from differential to single ended. CLKTX is divided by 3 or 4
output of the DAC sampling clock.
NCR2-113+ 2:1 impedance ratio transformer. Used to convert single-ended input clock to differential for the DAC.
Table 2. Jumpers on DAC38RF8xEVM
Jumper Default Position Description
JP1 Shunt pin 2-3 shunt pin1-2: Put some DAC internal blocks in sleep mode.
Shunt pin2-3: Take DAC out of sleep mode
JP2 Shunt pin 2-3 shunt pin1-2- Enable DAC output.
Shunt pin2-3-disable DAC output
JP3 Open Open: Disables power to the on-board 122.88 MHz VCXO (Y1). Leave open
when VCXO is not used
Closed: Enables power to the on-board 122.88 MHz VCXO
JP8 Open Open: Enables VDDDIG1 supply (U37).
Closed: disables VDDDIG1 supply (U37)
JP9 Open Open: Enables VEE18N supply (U19).
Closed: disables VEE18N supply (U19)
JP10 Shunt pin 1-2 Closed: Enable external clock mode
Open: Enable on-chip PLL clock mode
J11 Open Not used
J22 Open Provides access to externally monitor ATEST pin
J23 Shunt pin 1-2, 3-4, 5-6, 7-8 Connects DAC SPI interface to FT2232H (U4) spi interface.
1.2.1 Clocking Modes
The DAC38RF8xEVM may be configured into one of five clocking modes. These clocking modes are:
1. Direct External clock mode with high amplitude clock
2. Direct External clock mode with low amplitude clock (less than 7 dBm)
3. On-chip PLL clock mode
4. On-board VCXO clock mode
5. LMF = 413 or 823, 12-bits clock mode
1.2.1.1 Direct External Clock Mode With High Amplitude Clock (CMODE1)
This mode is intended for use with signal generators that can output 16 dBm or higher. Examples are
Keysight E8257D or R&S SMA100. To use this mode, the only modification from the default EVM
configuration is to connect a shunt between pin 1 and 2 of jumper JP10. Then, provide a 16-dBm clock to
SMA J1. This is shown in
Figure 2 . By default, the EVM is configured to use the single-ended clock input
of the DAC in this mode. For best spurious performance, also install C1, C333, and C334 on the EVM to
switch to differential clock input of DAC. Refer to the schematics and BOM of the EVM for the component
values (
SLAC734 ).