Texas Instruments DAC38RF80EVM, User Manual

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Introduction
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4 SLAU671A – October 2016 – Revised March 2017
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DAC38RF8xEVM
1.2.1.2 Direct External Clock Mode With Low Amplitude Clock (CMODE2)
The purpose of this mode is for use with monolithic clock synthesizers like the LMX259x . Clock power in
the range of 3 dBm to 7 dBm is recommended in this mode. Note that when using the LMX2592 with the
frequency doubler enabled, an external filter is required to attenuate the sub-harmonic at half the clock
frequency to –50 dBc or better. To configure the EVM in this mode from the default configuration:
1. Install SMA J27
2. Remove C2, C3, R215, R211
3. Install R323, R324, C449, C450 (refer to the schematics and BOM of the EVM for the component
values ( SLAC734 )
4. Connect the positive and negative output of clock synthesizer to SMA J27 and SMA J1, respectively
5. Remove jumper JP10
6. Use a second signal generator to provide a clock to SMA J4 and set the amplitude to 6 dBm. The
frequency of this clock is one-fourth of the sampling rate (or Fs/4). This clock is used to provide the
reference clock of the FPGA and SYSREF.
7. Connect SMA J24 to the reference input of the clock synthesizer. The frequency at SMA J24 is set
from the EVM GUI in a later step.
1.2.1.3 On-Chip PLL Clock Mode (CMODE3)
This mode is for evaluating the DAC performance with a low-frequency reference clock and the internal
PLL/VCO as the sampling clock. To use this mode, connect a clock at 6 dBm to SMA J4 and remove the
shunt connecting pin1 and 2 of jumper JP10. Keep all other hardware settings in the default configuration.
The frequency of the clock at SMA J4 is determined from the EVM GUI in a later step.
1.2.1.4 On-Board VCXO Clock Mode (CMODE4)
This mode allows the DAC to be evaluated without providing any external clock. The on-board VCXO
running at a fixed 122.88-MHz frequency can be used to provide a reference clock to the LMK04828 PLL.
The high-frequency clock generated by the LMK04828 PLL is subsequently divided down and used to
source reference clock and SYSREF to the DAC internal PLL and the FPGA on TSW14J56 EVM. To use
this mode, connect a shunt between pins 1 and 2 of jumper JP3. Keep all other hardware settings in the
default configuration.
1.2.1.5 LMF = 413 or 823, 12-Bits Clock Mode(CMODE5)
This mode is used to generate the required clocks for evaluating the DAC in 12-bits mode, LMF = 413 or
823 only. Two signal generators with their 10-MHz reference connected together are required in this
mode. The setup involves:
1. Provide an external sampling clock to SMA J1
2. Provide a second clock to SMA J4 with an amplitude of 6 dBm. The frequency of this clock will be
determined by the EVM GUI in a later step. Connect the reference of the two signal generators
together.
3. Remove the shunt on pins 1 and 2 of jumper JP10