Quick Start
9
SLAU671A – October 2016 – Revised March 2017
Copyright © 2016–2017, Texas Instruments Incorporated
DAC38RF8xEVM
Figure 7. DAC38RF83 EVM Setup for On-Chip PLL Mode
1. Connect a 5-V power supply to connector J21 (+5 V IN).
2. Connect a USB cable to the USB connector (J16).
3. Provide a 4–8 dBm external reference clock to SMA J4 as shown in
. The frequency of this
reference clock is set in a later step.
4. Connect a spectrum analyzer to the DAC output SMA connector.
2.1.5
DAC38RF8x Graphical User Interface (GUI)
1. Start the DAC38RF8xEVM GUI then navigate to the quick start page as shown in
.
2. Verify that the green USB Status indicator on the top right corner is lit. If it is not lit, click the
Reconnect FTDI?
button and check the
USB Status
indicator again.
3. On the
Quick Start
tab, toggle the
DAC RESETB Pin
button and then click the
Load Default
button.
The software automatically configures the DAC to its default state.
4. Check the
PLL Enable
box and enter the desired on-chip PLL reference clock frequency.
NOTE:
The
DAC Clock Frequency
box automatically updates based on the M, N, and Ref Freq
values entered. If the calculated DAC clock frequency is not supported by the on-chip PLL,
the
DAC Clock Frequency
box blinks.
For this example:
(a) If using DAC38RF80EVM, DAC38RF87EVM, or DAC38RF82EVM set the reference
frequency to 384 MHz, M = 4 and N = 1. The DAC PLL clock frequency is 6144 MHz.
(b) If using DAC38RF86EVM, set the reference frequency to 368.64 MHz, M = 6 and N = 1.
The DAC PLL clock frequency is 8847.36 MHz.
(c) If using DAC38RF89EVM, set the reference frequency to 307.2 MHz, M = 4 and N = 1.
The DAC PLL clock frequency is 4915.2 MHz.
5. Specify the desired number of DACs (Dual DAC), number of IQ pairs (1 IQ pair), number of lanes (4
