Texas Instruments Chipcon CC2420 ZDK PRO Manual Download Page 60 | Manualshive

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CC2420

SWRS041B Page 60 of 89

(

λ

/4). They are very easy to design and

can be implemented simply as a “piece of
wire” or even integrated into the PCB.

The length of the

λ

/4-monopole antenna is

given by:

L = 7125 / f

where f is in MHz, giving the length in cm.
An antenna for 2450 MHz should be 2.9
cm.

Non-resonant monopole antennas shorter
than

λ

/4 can also be used, but at the

expense of range. In size and cost critical
applications such an antenna may very
well be integrated into the PCB.

Enclosing the antenna in high dielectric
constant material reduces the overall size

of the antenna. Many vendors offer such
antennas intended for PCB mounting.

Helical antennas can be thought of as a
combination of a monopole and a loop
antenna. They are a good compromise in
size critical applications. Helical antennas
tend to be more difficult to optimize than
the simple monopole.

Loop antennas are easy to integrate into
the PCB, but are less effective due to
difficult impedance matching because of
their very low radiation resistance.

For low power applications the differential
antenna is recommended giving the best
range and because of its simplicity.

The antenna should be connected as
close as possible to the IC. If the antenna
is located away from the RF pins the
antenna should be matched to the feeding
transmission line (50

Ω

).

«
...
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59
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62
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»

Summary of Contents for Chipcon CC2420 ZDK PRO

Page 1: ...iming information These features reduce the load on the host controller and allow CC2420 to interface low cost microcontrollers The configuration interface and transmit receive FIFOs of CC2420 are accessed via an SPI interface In a typical application CC2420 will be used together with a microcontroller and a few external passive components CC2420 is based on Chipcon s SmartRF 03 technology in 0 18...

Page 2: ...ltage regulator__________________________________________________________19 9 5 Power supply decoupling and filtering _________________________________________19 10 IEEE 802 15 4 Modulation Format ____________________________________________24 11 Configuration Overview _____________________________________________________25 12 Evaluation Software ___________________________________________________...

Page 3: ...________________________________________________________________51 27 2 PLL self calibration________________________________________________________51 28 Output Power Programming _________________________________________________51 29 Voltage Regulator __________________________________________________________51 30 Battery Monitor____________________________________________________________52 31 Cry...

Page 4: ..._____________________________________85 41 Ordering Information _______________________________________________________85 42 General Information ________________________________________________________86 42 1 Document History _________________________________________________________86 42 2 Product Status Definitions___________________________________________________87 43 Address Information ______...

Page 5: ... Control HSSD High Speed Serial Debug IEEE Institute of Electrical and Electronics Engineers IF Intermediate Frequency ISM Industrial Scientific and Medical ITU T International Telecommunication Union Telecommunication Standardization Sector I O Input Output I Q In phase Quadrature phase kbps kilo bits per second LNA Low Noise Amplifier LO Local Oscillator LQI Link Quality Indication LSB Least Sig...

Page 6: ...ess Personal Area Networks LR WPANs http standards ieee org getieee802 download 802 15 4 2003 pdf 2 NIST FIPS Pub 197 Advanced Encryption Standard AES Federal Information Processing Standards Publication 197 US Department of Commerce N I S T November 26 2001 Available from the NIST website http csrc nist gov publications fips fips197 fips 197 pdf 3 R Housley D Whiting N Ferguson Counter with CBC M...

Page 7: ...passives No external filters needed Easy configuration interface 4 wire SPI interface Serial clock up to 10 MHz 802 15 4 MAC hardware support Automatic preamble generator Synchronisation word insertion detection CRC 16 computation and checking over the MAC payload Clear Channel Assessment Energy detection digital RSSI Link Quality Indication Full automatic MAC security CTR CBC MAC CCM 802 15 4 MAC...

Page 8: ...um ratings given above should under no circumstances be violated Stress exceeding one or more of the limiting values may cause permanent damage to the device Caution ESD sensitive device Precaution should be used when handling the device in order to prevent permanent damage 5 Operating Conditions Parameter Min Typ Max Units Condition Supply voltage for on chip voltage regulator VREG_IN pin 43 2 1 ...

Page 9: ...n 1 requires minimum 3 dBm Programmable output power range 24 dB The output power is programmable in 8 steps from approximately 24 to 0 dBm Harmonics 2 nd harmonic 3 rd harmonic 44 64 dBm dBm Measured conducted with 1 MHz resolution bandwidth on spectrum analyser At max output power delivered to a single ended 50 Ω load through a balun See page 54 Spurious emission 30 1000 MHz 1 12 75 GHz 1 8 1 9 ...

Page 10: ... as specified by 1 1 requires 30 dB Alternate channel rejection 10 MHz channel spacing 53 dB Wanted signal 82 dBm adjacent modulated channel at 10 MHz PER 1 as specified by 1 1 requires 30 dB Channel rejection 15 MHz 15 MHz 62 62 dB dB Wanted signal 82 dBm Undesired signal is an IEEE 802 15 4 modulated channel stepped through all channels from 2405 to 2480 MHz Signal level for PER 1 Co channel rej...

Page 11: ...eiver 6 4 RSSI Carrier Sense Parameter Min Typ Max Unit Condition Note Carrier sense level 77 dBm Programmable in RSSI CCA_THR RSSI dynamic range 100 dB The range is approximately from 100 dBm to 0 dBm RSSI accuracy 6 dB See page 48 for details RSSI linearity 3 dB RSSI average time 128 µs 8 symbol periods as specified by 1 6 5 IF Section Parameter Min Typ Max Unit Condition Note Intermediate frequ...

Page 12: ...puts Parameter Min Typ Max Unit Condition Note General Signal levels are referred to the voltage level at pin DVDD3 3 Logic 0 input voltage 0 0 3 DVDD V Logic 1 input voltage 0 7 DVDD DVDD V Logic 0 output voltage 0 0 4 V Output current 8 mA 3 3 V supply voltage Logic 1 output voltage 2 5 VDD V Output current 8 mA 3 3 V supply voltage Logic 0 input current NA 1 µA Input signal equals GND Logic 1 i...

Page 13: ...dition Note Current consumption 6 30 90 µA When enabled Start up time 100 µs Voltage regulator already enabled Settling time 2 µs New toggle voltage programmed Step size 50 mV Hysteresis 10 mV Absolute accuracy 80 80 mV May be software calibrated for known reference voltage Relative accuracy 50 50 mV 6 10 Power Supply Parameter Min Typ Max Unit Condition Note Current consumption in different modes...

Page 14: ...Typ Max Unit Condition Note Current Consumption transmit mode P 25 dBm P 15 dBm P 10 dBm P 5 dBm P 0 dBm 8 5 9 9 11 14 17 4 mA mA mA mA mA The output power is delivered differentially to a 50 Ω singled ended load through a balun see also page 54 ...

Page 15: ...ARD Power analog Connection of guard ring for VCO to AVDD shielding 2 AVDD_VCO Power analog 1 8 V Power supply for VCO 3 AVDD_PRE Power analog 1 8 V Power supply for Prescaler 4 AVDD_RF1 Power analog 1 8 V Power supply for RF front end 5 GND Ground analog Grounded pin for RF shielding 6 RF_P RF I O Positive RF input output signal to LNA from PA in receive transmit mode 7 TXRX_SWITCH Power analog C...

Page 16: ...ut SPI Chip select active low 32 SCLK Digital input SPI Clock input up to 10 MHz 33 SI Digital input SPI Slave Input Sampled on the positive edge of SCLK 34 SO Digital output tristate SPI Slave Output Updated on the negative edge of SCLK Tristate when CSn high 35 DVDD_RAM Power digital 1 8 V Power supply for digital RAM 36 NC Not Connected 37 AVDD_XOSC16 Power analog 1 8 V crystal oscillator power...

Page 17: ... indicates that a start of frame delimiter has been detected CC2420 buffers the received data in a 128 byte receive FIFO The user may read the FIFO through an SPI interface CRC is verified in hardware RSSI and correlation values are appended to the frame CCA is available on a pin in receive mode Serial unbuffered data modes are also available for test purposes The CC2420 transmitter is based on di...

Page 18: ... the synthesizer A digital lock signal is available from the PLL The digital baseband includes support for frame handling address recognition data buffering and MAC security The 4 wire SPI serial interface is used for configuration and data buffering An on chip voltage regulator delivers the regulated 1 8 V supply voltage The voltage regulator may be enabled disabled through a separate pin A batte...

Page 19: ...e balun in Figure 4 consists of C61 C62 C71 C81 L61 L62 and L81 and will present the optimum RF termination to CC2420 with a 50 Ω load on the antenna connection A low pass filter may be added to add margin to the FCC requirement on second harmonic level If a balanced antenna such as a folded dipole is used the balun can be omitted If the antenna also provides a DC path from the TXRX_SWITCH pin to ...

Page 20: ...nents 35 34 33 32 31 30 29 28 27 26 25 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 QLP48 7x7 CC2420 RF Transceiver DSUB_CORE DSUB_PADS AVDD_ADC DVDD_ADC DGUARD AVDD_IF2 DGND_GUARD AVDD_RF2 DGND NC NC RESETn RF_P RF_N AVDD_PRE AVDD_RF1 TXRX_SWITCH AVDD_VCO VCO_GUARD AVDD_SW GND GND NC NC VREG_OUT AVDD_CHP R_BIAS AVDD_IF1 VREG_IN VREG_EN XOSC...

Page 21: ...ARD AVDD_RF2 DGND NC NC RESETn RF_P RF_N AVDD_PRE AVDD_RF1 TXRX_SWITCH AVDD_VCO VCO_GUARD AVDD_SW GND GND NC NC VREG_OUT AVDD_CHP R_BIAS AVDD_IF1 VREG_IN VREG_EN XOSC16_Q1 XOSC16_Q2 ATEST2 ATEST1 NC AVDD_XOSC16 CSn FIFO FIFOP CCA SFD DVDD1 8 SCLK DVDD_RAM SI SO DVDD3 3 NC XTAL C391 C381 C61 C71 C62 Antenna 50 Ohm L81 C81 L62 Digital Interface R451 3 3 V Power supply L61 C42 Figure 4 Typical applic...

Page 22: ...2 DGND_GUARD AVDD_RF2 DGND NC NC RESETn RF_P RF_N AVDD_PRE AVDD_RF1 TXRX_SWITCH AVDD_VCO VCO_GUARD AVDD_SW GND GND NC NC VREG_OUT AVDD_CHP R_BIAS AVDD_IF1 VREG_IN VREG_EN XOSC16_Q1 XOSC16_Q2 ATEST2 ATEST1 NC AVDD_XOSC16 CSn FIFO FIFOP CCA SFD DVDD1 8 SCLK DVDD_RAM SI SO DVDD3 3 NC XTAL C391 C381 Digital Interface R451 3 3 V Power supply L61 C42 Folded dipole antenna L71 Figure 5 Suggested applicat...

Page 23: ...F 5 NP0 0402 C391 27 pF 5 NP0 0402 27 pF 5 NP0 0402 27 pF 5 NP0 0402 L61 8 2 nH 5 Monolithic multilayer 0402 7 5 nH 5 Monolithic multilayer 0402 27 nH 5 Monolithic multilayer 0402 L62 Not used 5 6 nH 5 Monolithic multilayer 0402 Not used L71 22 nH 5 Monolithic multilayer 0402 Not used 12 nH 5 Monolithic multilayer 0402 L81 1 8 nH 0 3nH Monolithic multilayer 0402 7 5 nH 5 Monolithic multilayer 0402...

Page 24: ...0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 2 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 3 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 4 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 5 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 6 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 7 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 ...

Page 25: ...on Overview CC2420 can be configured to achieve the best performance for different applications Through the programmable configuration registers the following key parameters can be programmed Receive transmit mode RF channel selection RF output power Power down power up mode Crystal oscillator power up power down Clear Channel Assessment mode Packet handling hardware support Encryption Authenticat...

Page 26: ...ith a software program SmartRF Studio Windows interface which may be used for radio performance and functionality evaluation SmartRF Studio can be downloaded from TI s web page http www ti com Figure 8 shows the user interface of the CC2420 configuration software Figure 8 SmartRF Studio user interface ...

Page 27: ... sent on the SI line The CSn pin Chip Select active low must be kept low during this transfer The bit to be sent first is the RAM Register bit set to 0 for register access followed by the R W bit 0 for write 1 for read The following 6 bits are the address bits A5 0 A5 is the most significant bit of the address and is sent first The 16 data bits are then transferred D15 0 also MSB first See Figure ...

Page 28: ...Min Max Units Conditions SCLK clock frequency FSCLK 10 MHz SCLK low pulse duration tcl 25 ns The minimum time SCLK must be low SCLK high pulse duration tch 25 ns The minimum time SCLK must be high CSn setup time tsp 25 ns The minimum time CSn must be low before the first positive edge of SCLK CSn hold time tns 25 ns The minimum time CSn must be held low after the last negative edge of SCLK SI setu...

Page 29: ...crystal oscillator enable receive mode start decryption etc All 15 command strobes are listed in Table 11 on page 62 When the crystal oscillator is disabled Power Down state in Figure 25 on page 44 only the SXOSCON command strobe may be used All other command strobes will be ignored and will have no effect The crystal oscillator must stabilise see the XOSC16M_STABLE status bit in Table 5 before ot...

Page 30: ... for FIFO write operations because the FIFO counter will not be updated Use RXFIFO and TXFIFO access instead as described in section FIFO access As with register data data stored in RAM will be retained during power down mode but not when the power supply is turned off e g by disabling the voltage regulator using the VREG_EN pin ADDR CSn Command strobe Read or write a whole register 16 bit DATA8MS...

Page 31: ...AM access The RXFIFO is both writeable and readable Writing to the RXFIFO should however only be done for debugging or for using the RXFIFO for security operations decryption authentication The crystal oscillator must be running when accessing the FIFOs When writing to the TXFIFO the status byte see Table 5 is output for each new data byte on SO as shown in Figure 9 This could be used to detect TX...

Page 32: ...cularly for beaconing networks 14 1 Configuration interface A CC2420 to microcontroller interface example is shown in Figure 12 The microcontroller uses 4 I O pins for the SPI configuration interface SI SO SCLK and CSn SO should be connected to an input at the microcontroller SI SCLK and CSn must be microcontroller outputs Preferably the microcontroller should have a hardware SPI interface The mic...

Page 33: ...lly flushed by CC2420 if it fails address recognition This may be handled by using the FIFOP pin since this pin does not go active until the frame passes address recognition Figure 14 shows an example of pin activity when reading a packet from the RXFIFO In this example the packet size is 8 bytes IOCFG0 FIFOP_THR 3 and MODEMCTRL0 AUTOCRC is set The length will be 8 bytes RSSI will contain the aver...

Page 34: ...f bytes FIFO P_TH R FCS Corr Figure 14 Example of pin activity when reading RXFIFO 14 4 Transmit mode During transmit the FIFO and FIFOP pins are still only related to the RXFIFO The SFD pin is however active during transmission of a data frame as shown in Figure 15 The SFD pin goes active when the SFD field has been completely transmitted It goes inactive again when the complete MPDU as defined b...

Page 35: ...tor Symbol Synchroniser and Data Decision The block diagram for the CC2420 demodulator is shown in Figure 16 Channel filtering and frequency offset compensation is performed digitally The signal level in the channel is estimated to generate the RSSI level see the RSSI Energy Detection section on page 48 for more information Data filtering is also included for enhanced performance With the 40 ppm f...

Page 36: ...able The default values are compliant with 1 Changing these values will make the system non compliant to IEEE 802 15 4 A synchronisation header is always transmitted first in all transmit modes The preamble sequence length can be set by MDMCTRL0 PREAMBLE_LENGTH while the SFD is programmed in the SYNCWORD register SYNCWORD is 2 bytes long which gives the user some extra flexibility as described bel...

Page 37: ...ero symbols 0 0 0 0 0 0 0 SW0 SW0 SYNCWORD 3 0 SW1 SYNCWORD 7 4 SW2 SYNCWORD 11 8 SW3 SYNCWORD 15 12 SW1 SW2 SW3 if different from F else 0 if different from F else 0 if different from F else 0 if different from F else 0 Synchronisation Header Each box corresponds to 4 bits Hence the preamble corresponds to 8 x 4 0 s or 4 bytes with the value 0 Figure 18 Transmitted Synchronisation Header 16 2 Len...

Page 38: ...ended at the correct position defined by the length field The FCS is not written to the TXFIFO but stored in a separate 16 bit register In receive mode the FCS is verified by hardware The user is normally only interested in the correctness of the FCS not the FCS sequence itself The FCS sequence itself is therefore not written to the RXFIFO during receive Instead when MODEMCTRL0 AUTOCRC is set the ...

Page 39: ...s busy See the Clear Channel Assessment section on page 50 for details on CCA The preamble sequence is started 12 symbol periods after the command strobe After the programmable start of frame delimiter has been transmitted data is fetched from the TXFIFO A TXFIFO underflow is issued if too few bytes are written to the TXFIFO Transmission is then automatically stopped The underflow is indicated in ...

Page 40: ...2 In serial transmit mode MDMCTRL1 TX_MODE 1 a synchronisation sequence is inserted at the start of each frame by hardware as in buffered mode Data is sampled by CC2420 on the positive edge of FIFOP and should be updated by the microcontroller on the negative edge of FIFOP See Figure 22 for an illustration of the timing in serial transmit mode The SFD and CCA pins retain their normal operation als...

Page 41: ...ted frame is flushed data from previously accepted frames may still be in the RXFIFO The IOCFG0 BCN_ACCEPT control bit must be set when the PAN identifier programmed into CC2420 RAM is equal to 0xFFFF and cleared otherwise This particularly applies to active and passive scans as defined by 1 which requires all received beacons to be processed by the MAC sublayer Incoming frames with reserved frame...

Page 42: ...l periods at least 12 symbol periods after the last symbol of the incoming frame This timing must be controlled by the microcontroller by issuing the SACK and SACKPEND command strobe 12 symbol periods before the following backoff slot boundary as illustrated in Figure 24 If a SACK or SACKPEND command strobe is issued while receiving an incoming frame the acknowledge frame is transmitted 12 symbol ...

Page 43: ...status register returned during address transfer indicates whether the oscillator is running and stable or not see Table 5 This status register can be polled when waiting for the oscillator to start For test purposes the frequency synthesizer FS can also be manually calibrated and started by using the STXCAL command strobe register This will not start a transmission before a STXON command strobe i...

Page 44: ...transmitted RX_CALIBRATE 2 and 40 T r a n s m i s s i o n c o m p l e t e d S R X O N RX_SFD_SEARCH 3 4 5 and 6 RX_FRAME 16 and 40 12 symbol periods later SFD found Frame received or failed address recognition Automatic or manual acknowledge request TX_ACK_CALIBRATE 48 12 symbol periods later TX_ACK_PREAMBLE 49 50 and 51 TX_ACK 52 53 and 54 Acknowledge completed RX_OVERFLOW 17 Crystal oscillator d...

Page 45: ...eys individually in the SEC_TXKEYSEL SEC_RXKEYSEL and SEC_SAKEYSEL control bits SECCTRL0 As can be seen from Table 6 on page 31 KEY0 is located from address 0x100 and KEY1 from address 0x130 A way of establishing the keys used for encryption and authentication must be decided for each particular application IEEE 802 15 4 does not define how this is done it is left to the higher layer of the protoc...

Page 46: ... written at the same time as reading out the previous ciphertext 21 4 In line security operations CC2420 can do MAC security operations encryption decryption and authentication on frames within the TXFIFO and RXFIFO These operations are called in line security operations As with other MAC hardware support within CC2420 in line security operation relies on the length field in the PHY header A corre...

Page 47: ...TXFIFO is then encrypted as specified by 1 The encryption module will encrypt all the plaintext currently available and wait if not everything is pre buffered The encryption operation may also be started without any data in the TXFIFO at all and data will be encrypted as it is written to the TXFIFO When decryption is initiated with a SRXDEC command strobe the ciphertext of the RXFIFO is then decry...

Page 48: ... providing a digital value that can be read from the 8 bit signed 2 s complement RSSI RSSI_VAL register The RSSI value is always averaged over 8 symbol periods 128 µs in accordance with 1 The RSSI_VALID status bit Table 5 indicates when the RSSI value is valid meaning that the receiver has been enabled for at least 8 symbol periods The RSSI register value RSSI RSSI_VAL can be referred to the power...

Page 49: ...though it actually reduces the true link quality CC2420 therefore also provides an average correlation value for each incoming packet based on the 8 first symbols following the SFD This unsigned 7 bit value can be looked upon as a measurement of the chip error rate although CC2420 does not do chip decision As described in the Frame check sequence section on page 38 the average correlation value fo...

Page 50: ...A is active high but the polarity may be changed by setting the IOCFG0 CCA_POLARITY control bit Implementing CSMA CA may easiest be done by using the STXONCCA command strobe as described in the Radio control state machine section on page 43 Transmission will then only start if the channel is clear The TX_ACTIVE status bit see Table 5 may be used to detect the result of the CCA 26 Frequency and Cha...

Page 51: ... 31 0xA0FF 0 17 4 27 0xA0FB 1 16 5 23 0xA0F7 3 15 2 19 0xA0F3 5 13 9 15 0xA0EF 7 12 5 11 0xA0EB 10 11 2 7 0xA0E7 15 9 9 3 0xA0E3 25 8 5 Table 9 Output power settings and typical current consumption 2 45 GHz 29 Voltage Regulator CC2420 includes a low drop out voltage regulator This is used to provide a 1 8 V power supply to the CC2420 power supplies The voltage regulator should not be used to provi...

Page 52: ...G_EN Regulator Enable disable Figure 28 Voltage regulator simplified schematic 30 Battery Monitor The on chip battery monitor enables monitoring the unregulated voltage on the VREG_IN pin It gives status information on the voltage being above or below a programmable threshold A simplified schematic of the battery monitor is shown in Figure 29 VREG_IN Internal bandgap voltage reference 1 25 V BATTM...

Page 53: ...r the data rate as well as other internal signal processing functions other frequencies cannot be used If an external clock signal is used this should be connected to XOSC16_Q1 while XOSC16_Q2 should be left open The MAIN XOSC16M_BYPASS bit must be set when an external clock signal is used Using the internal crystal oscillator the crystal must be connected between the XOSC16_Q1 and XOSC16_Q2 pins ...

Page 54: ...required for a single ended connector or a single ended antenna a balun should be used for optimum performance The balun adds the signals from the RF_N and RF_P This is achieved having two paths with equal amplitude response but 180 degrees phase difference 33 Transmitter Test Modes CC2420 can be set into different transmit test modes for performance evaluation The test mode descriptions in the fo...

Page 55: ...itted data sequence is then Synchronisation header 0x00 0x78 0xb8 0x4b 0x99 0xc3 0xe9 Since a synchronisation header preamble and SFD is transmitted in all TX modes this test mode may also be used to transmit a known pseudorandom bit sequence for bit error testing Please note that CC2420 requires symbol synchronisation not only bit synchronisation for correct reception Packet error rate is therefo...

Page 56: ...of 89 A Unit dBm RF Att 30 dB Ref Lvl 0 dBm Ref Lvl 0 dBm SWT 5 ms Center 2 45 GHz Span 10 MHz 1 MHz 1AVG 1SA RBW 100 kHz VBW 100 kHz 90 80 70 60 50 40 30 20 10 100 0 Date 23 OCT 2003 21 34 19 Figure 32 Modulated spectrum plot ...

Page 57: ...nly 20 40 kbps are available CC2420 may be powered up a smaller portion of the time so that the average power consumption is reduced for a given amount of data to be transferred 34 3 Crystal accuracy and drift A crystal accuracy of 40 ppm is required for compliance with IEEE 802 15 4 1 This accuracy must also take ageing and temperature drift into consideration A crystal with low temperature drift...

Page 58: ...e as the bit sequence which is output by CC2420 When operating at or below the sensitivity limit CC2420 may loose symbol synchronisation in infinite receive mode A new SFD and restart of the receiver may be required to re gain synchronisation In an IEEE 802 15 4 system all communication is based on packets The sensitivity limit specified by 1 is based on Packet Error Rate PER measurements instead ...

Page 59: ...or grounding and must be well connected to the ground plane with several vias The ground pins should be connected to ground as close as possible to the package pin using individual vias The de coupling capacitors should also be placed as close as possible to the supply pins and connected to the ground plane by separate vias Supply power filtering is very important The external components should be...

Page 60: ...l size of the antenna Many vendors offer such antennas intended for PCB mounting Helical antennas can be thought of as a combination of a monopole and a loop antenna They are a good compromise in size critical applications Helical antennas tend to be more difficult to optimize than the simple monopole Loop antennas are easy to integrate into the PCB but are less effective due to difficult impedanc...

Page 61: ...FIFO and RAM access During address transfer and while data is being written to the TXFIFO a status byte is returned on the serial data output pin SO This status byte is described in Table 5 on page 29 All configuration and status registers are described in the tables following Table 11 Address Register Register type Description 0x00 SNOP S No Operation has no other effect than reading out status b...

Page 62: ...R W Manufacturer ID Low 16 bits 0x1F MANFIDH R W Manufacturer ID High 16 bits 0x20 FSMTC R W Finite State Machine Time Constants 0x21 MANAND R W Manual signal AND override register 0x22 MANOR R W Manual signal OR override register 0x23 AGCCTRL R W AGC Control Register 0x24 AGCTST0 R W AGC Test Register 0 0x25 AGCTST1 R W AGC Test Register 1 0x26 AGCTST2 R W AGC Test Register 2 0x27 FSTST0 R W Freq...

Page 63: ...module Test purposes only 13 DEMOD_RESETn 1 R W Active low reset of the demodulator module Test purposes only 12 MOD_RESETn 1 R W Active low reset of the modulator module Test purposes only 11 FS_RESETn 1 R W Active low reset of the frequency synthesizer module Test purposes only 10 1 0 W0 Reserved write as 0 0 XOSC16M_BYPASS 0 R W Bypasses the crystal oscillator and uses a buffered version of the...

Page 64: ... CCA Hysteresis in dB values 0 through 7 dB 7 6 CCA_MODE 1 0 3 R W 0 Reserved 1 CCA 1 when RSSI_VAL CCA_THR CCA_HYST CCA 0 when RSSI_VAL CCA_THR 2 CCA 1 when not receiving valid IEEE 802 15 4 data CCA 0 otherwise 3 CCA 1 when RSSI_VAL CCA_THR CCA_HYST and not receiving valid IEEE 802 15 4 data CCA 0 when RSSI_VAL CCA_THR or receiving a packet 5 AUTOCRC 1 R W In packet mode a CRC 16 ITU T is calcul...

Page 65: ...om CRC infinite transmission For lab testing only 1 0 RX_MODE 1 0 0 R W Set test mode of RX 0 Buffered mode use RXFIFO normal operation 1 Receive serial mode output received data on pins Infinite RX For lab testing only 2 RXFIFO looping ignore overflow in RXFIFO and write cyclic infinite reception For lab testing only 3 Reserved RSSI 0x13 RSSI and CCA Status and Control Register Bit Field Name Res...

Page 66: ...ol Register Bit Field Name Reset R W Description 15 14 TXMIXBUF_CUR 1 0 2 R W TX mixer buffer bias current 0 690uA 1 980uA 2 1 16mA nominal 3 1 44mA 13 TX_TURNAROUND 1 R W Sets the wait time after STXON before transmission is started 0 8 symbol periods 128 us 1 12 symbol periods 192 us 12 11 TXMIX_CAP_ARRAY 1 0 0 R W Selects varactor array settings in the transmit mixers 10 9 TXMIX_CURRENT 1 0 0 R...

Page 67: ...mpensation current Nominal 3 1000 µA compensation current 9 8 MED_LNA_GAIN 1 0 2 R W Controls current in the LNA gain compensation branch in AGC Med gain mode 7 6 LOW_LNA_GAIN 1 0 3 R W Controls current in the LNA gain compensation branch in AGC Low gain mode 5 4 HIGH_LNA_CURRENT 1 0 2 R W Controls main current in the LNA in AGC High gain mode 0 240 µA LNA current x2 1 480 µA LNA current x2 2 640 ...

Page 68: ... mode 9 HIGH_HGM 1 R W RX Mixers high gain mode setting in AGC high gain mode 8 MED_HGM 0 R W RX Mixers high gain mode setting in AGC medium gain mode 7 6 LNA_CAP_ARRAY 1 0 1 R W Selects varactor array setting in the LNA 0 OFF 1 0 1pF x2 Nominal 2 0 2pF x2 3 0 3pF x2 5 4 RXMIX_TAIL 1 0 1 R W Control of the receiver mixers output current 0 12 µA 1 16 µA Nominal 2 20 µA 3 24 µA 3 2 RXMIX_VCM 1 0 1 R...

Page 69: ...ration status 1 when calibration in progress and 0 otherwise 11 LOCK_LENGTH 0 R W Synchronisation window pulse width 0 2 prescaler clock periods recommended 1 4 prescaler clock periods 10 LOCK_STATUS 0 R Frequency synthesizer lock status 0 Frequency synthesizer is out of lock 1 Frequency synthesizer is in lock 9 0 FREQ 9 0 357 2405 MHz R W Frequency control word controlling the RF operating freque...

Page 70: ...nto CBC MAC 1 Use the length of the data to be authenticated calculated as the packet length field SEC_TXL 2 for TX or using SEC_RXL for RX as the first byte into CBC MAC before the first data byte This bit should be set high for CBC MAC 802 15 4 inline security 7 SEC_SAKEYSEL 1 R W Stand Alone Key select 0 Key 0 is used 1 Key 1 is used 6 SEC_TXKEYSEL 1 R W TX Key select 0 Key 0 is used 1 Key 1 is...

Page 71: ...text bytes between length byte and the first byte to be decrypted CBC MAC Number of cleartext bytes between length byte and the first byte to be authenticated CCM l a defining the number of bytes to be authenticated but not decrypted Stand alone SEC_RXL has no effect BATTMON 0x1B Battery Monitor Control register Bit Field Name Reset R W Description 15 7 0 W0 Reserved write as 0 6 BATTMON_OK 1 R Ba...

Page 72: ...64 R W FIFOP_THR sets the threshold in number of bytes in the RXFIFO for FIFOP to go active IOCFG1 0x1D I O Configuration Register 1 Bit Field Name Reset R W Description 15 13 0 W0 Reserved write as 0 12 10 HSSD_SRC 2 0 0 R W The HSSD module is used as follows 0 Off 1 Output AGC status gain setting peak detector status accumulator value 2 Output ADC I and Q values 3 Output I Q after digital down m...

Page 73: ...en the time the RX chain is enabled and the demodulator and AGC is enabled The RX chain is started when the bandpass filter has been calibrated after 6 5 symbol periods 12 10 TC_SWITCH2TX 2 0 6 R W The time in advance the RXTX switch is set high before enabling TX In µs 9 6 TC_PAON2TX 3 0 10 R W The time in advance the PA is powered up before enabling TX In µs 5 3 TC_TXEND2SWITCH 2 0 2 R W The tim...

Page 74: ...Powerdown control of complex bandpass receive filter calibration oscillator 5 CHP_PD 1 R W Powerdown control of charge pump 4 FS_PD 1 R W Powerdown control of VCO I Q generator LO buffers 3 ADC_PD 1 R W Powerdown control of the ADCs 2 VGA_PD 1 R W Powerdown control of the VGA 1 RXBPF_PD 1 R W Powerdown control of complex bandpass receive filter 0 LNAMIX_PD 1 R W Powerdown control of LNA down conve...

Page 75: ...s receive filter calibration oscillator 5 CHP_PD 0 R W Powerdown control of charge pump 4 FS_PD 0 R W Powerdown control of VCO I Q generator LO buffers 3 ADC_PD 0 R W Powerdown control of the ADCs 2 VGA_PD 0 R W Powerdown control of the VGA 1 RXBPF_PD 0 R W Powerdown control of complex bandpass receive filter 0 LNAMIX_PD 0 R W Powerdown control of LNA down conversion mixers and front end bias AGCC...

Page 76: ... VGA stages when set 12 11 AGC_SETTLE_WAIT 1 0 1 R W Timing for AGC to wait for analog gain to settle 10 8 AGC_PEAK_DET_MODE 2 0 0 R W Sets the AGC mode for use of the VGA peak detectors Bit 2 Digital ADC peak detector enable disable Bit 1 Analog fixed stages peak detector enable disable Bit 0 Analog variable gain stage peak detector enable disable 7 6 AGC_WIN_SIZE 1 0 1 R W Window size for the ac...

Page 77: ...the time allowed for VCO frequency measurements during VCO calibration 0 PLL Calibration time is 37 us 1 PLL Calibration time is 57 us 13 10 VCO_CURRENT_REF 3 0 4 R W The value of the reference current calibrated against during VCO calibration 9 4 VCO_CURRENT_K 5 0 0 R W VCO current calibration constant Current B override value when FSTST2 VCO_CURRENT_OE 1 3 VC_DAC_EN 0 R W Controls the source of ...

Page 78: ...mplete The current is stepped down periodically with intervals as defined in CHP_STEP_PERIOD 3 0 START_CHP_CURRENT 3 0 13 R W The charge pump current to start with after VCO calibration is complete The current is then stepped down periodically to the value STOP_CHP_CURRENT with intervals as defined in CHP_STEP_PERIOD Also used for overriding the charge pump current when CHP_CURRENT_OE 1 RXBPFTST 0...

Page 79: ...scription 15 0 W0 Reserved write as 0 14 12 DAC_SRC 2 0 0 R W The TX DACs data source is selected by DAC_SRC according to 0 Normal operation from modulator 1 The DAC_I_O and DAC_Q_O override values below 2 From ADC most significant bits 3 I Q after digital down mixing and channel filtering 4 Full spectrum White Noise from CRC 5 From ADC least significant bits 6 RSSI Cordic Magnitude Output 7 HSSD ...

Page 80: ...to ADC 4 Outputs I ATEST1 and Q ATEST2 from LPF 5 Inputs I ATEST2 and Q ATEST1 to TxMIX 6 Outputs P ATEST1 and N ATEST2 from Prescaler Must be terminated externally 7 Connects TX IF to RX IF and simultaneously the ATEST1 pin to the internal VC node see VC_IN_TEST_EN 8 Connect ATEST1 input to ATEST2 output through single2diff and diff2single buffers used for measurements on the test interface RESER...

Page 81: ...ilter power down active high 10 FFCTRL_LNAMIX_PD Receiver LNA Mixer power down active high 11 FFCTRL_PA_P_PD Power amplifier power down active high 12 AGC_UPDATE High one 16 MHz clock cycle each time the AGC updates its gain setting 13 VGA_PEAK_DET 1 VGA Peak detector gain stage 1 14 VGA_PEAK_DET 3 VGA Peak detector gain stage 3 15 AGC_LNAMIX_GAINMODE 1 RF receiver front end gain mode bit 1 16 AGC...

Page 82: ...r LNA Mixer power down active high 11 FFCTRL_PA_P_PD Power amplifier power down active high 12 VGA_PEAK_DET 0 VGA Peak detector gain stage 0 13 VGA_PEAK_DET 2 VGA Peak detector gain stage 2 14 VGA_PEAK_DET 4 VGA Peak detector gain stage 4 15 AGC_LNAMIX_GAINMODE 0 RF receiver front end gain mode bit 0 16 AGC_VGA_GAIN 0 VGA gain setting bit 0 17 RXBPF_CAL_CLK Receiver bandpass filter calibration clo...

Page 83: ... and not to scale Quad Leadless Package QLP D D1 E E1 e b L D2 E2 QLP 48 Min Max 6 9 7 0 7 1 6 65 6 75 6 85 6 9 7 0 7 1 6 65 6 75 6 85 0 5 0 18 0 30 0 3 0 4 0 5 5 05 5 10 5 15 5 05 5 10 5 15 The overall packet height is 0 85 0 05 All dimensions in mm The package is compliant to JEDEC standard MO 220 ...

Page 84: ...le There are nine 14 mil diameter via holes distributed symmetrically in the ground pad under the package See also the CC2420 EM reference design 40 1 Package thermal properties Thermal resistance Air velocity m s 0 Rth j a K W 25 6 40 2 Soldering information Recommended soldering profile is according to IPC JEDEC J STD 020C ...

Page 85: ...43 tube CC2420 RTR1 CC2420RTCR Single chip RF Transceiver CC2420 QLP48 package RoHS compliant Pb free assembly T R with 4000 pcs per reel 4000 tape and reel CC2420Z RTB1 CC2420ZRTC Single chip RF Transceiver including royalty for using TI s ZigBee Software Stack Z Stack in an end product CC2420 QLP48 package RoHS compliant Pb free assembly in tubes with 43 pcs per tube 43 tube CC2420Z RTR1 CC2420Z...

Page 86: ...pdated address information Added new balun circuit with transmission lines in section Application Circuit Updated electrical specifications with measured data on CC2420 EM with new balun Updated values and figure for suggested application circuit with folded dipole antenna Corrected values for capacitors in Table 2 discrete balun Added data latency figure in receiver specification Updated crystal ...

Page 87: ... drawing Included layout drawing for package Power supply pins defined clearer in Absolute maximum ratings Third harmonic level corrected to 51dBm in Electrical specifications second harmonic to 37dBm Table with Crystal oscillator component values corrected Link to reference 3 corrected Corrected spelling grammar and references to tables and figures Figure showing SmartRF Studio user interface inc...

Page 88: ...Fax 1 972 927 6377 Internet Email support ti com sc pic americas htm Europe Middle East and Africa Phone Belgium English 32 0 27 45 54 32 Finland English 358 0 9 25173948 France 33 0 1 30 70 11 64 Germany 49 0 8161 80 33 11 Israel English 180 949 0107 Italy 800 79 11 37 Netherlands English 31 0 546 87 95 45 Russia 7 0 95 363 4824 Spain 34 902 35 40 28 Sweden English 46 0 8587 555 22 United Kingdom...

Page 89: ...41 India 91 80 51381665 Toll Indonesia 001 803 8861 1006 Korea 080 551 2804 Malaysia 1 800 80 3973 New Zealand 0800 446 934 Philippines 1 800 765 7404 Singapore 800 886 1028 Taiwan 0800 006800 Thailand 001 800 886 0010 Fax 886 2 2378 6808 Email tiasia ti com or ti china ti com Internet support ti com sc pic asia htm 2007 Texas Instruments All rights reserved ...

Page 90: ...siness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necess...

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