CC2420
SWRS041B Page 31 of 89
Address
Byte Ordering
Name
Description
0x16F –
0x16C
- -
Not
used
0x16B –
0x16A
MSB
LSB
SHORTADR
16-bit Short address, used for address recognition.
0x169 –
0x168
MSB
LSB
PANID
16-bit PAN identifier, used for address recognition.
0x167 –
0x160
MSB
LSB
IEEEADR
64-bit IEEE address of current node, used for address
recognition.
0x15F –
0x150
MSB
LSB
CBCSTATE
Temporary storage for CBC-MAC calculations
0x14F –
0x140
MSB (Flags)
LSB
TXNONCE / TXCTR
Transmitter nonce for in-line authentication and
transmitter counter for in-line encryption.
0x13F –
0x130
MSB
LSB
KEY1
Encryption key 1
0x12F –
0x120
MSB
LSB
SABUF
Stand-alone encryption buffer, for plaintext input and
ciphertext output
0x11F –
0x110
MSB (Flags)
LSB
RXNONCE / RXCTR
Receiver nonce for in-line authentication or
receiver counter for in-line decryption.
0x10F –
0x100
MSB
LSB
KEY0
Encryption key 0
0x0FF –
0x080
MSB
LSB
RXFIFO
128 bytes receive FIFO
0x07F –
0x000
MSB
LSB
TXFIFO
128 bytes transmit FIFO
Table 6.
CC2420
RAM Memory Space
13.6 FIFO
access
The TXFIFO and RXFIFO may be
accessed through the TXFIFO (0x3E) and
RXFIFO (0x3F) registers.
The TXFIFO is write only, but may be read
back using RAM access as described in
the previous section. Data is read and
written one byte at a time, as with RAM
access. The RXFIFO is both writeable and
readable. Writing to the RXFIFO should
however only be done for debugging or for
using the RXFIFO for security operations
(decryption / authentication).
The crystal oscillator must be running
when accessing the FIFOs.
When writing to the TXFIFO, the status
byte (see Table 5) is output for each new
data byte on
SO
, as shown in Figure 9.
This could be used to detect TXFIFO
underflow (see section RF Data Buffering
section on page 39) while writing data to
the TXFIFO.
Multiple FIFO bytes may be accessed in
one operation, as with the RAM access.
FIFO access can only be terminated by
setting the
CSn
pin high once it has been
started.
The
FIFO
and
FIFOP
pins also provide
additional information on the data in the
receive FIFO, as will be described in the
Microcontroller Interface and Pin
Description section on page 32. Note that
the
FIFO
and
FIFOP
pins only apply to
the RXFIFO. The TXFIFO has its
underflow flag in the status byte.
The TXFIFO may be flushed by issuing a
SFLUSHTX
command strobe. Similarly, a
SFLUSHRX
command strobe will flush the
receive FIFO.
13.7 Multiple SPI access
Register access, command strobes, FIFO
access and RAM access may be issued
continuously without setting
CSn
high.
E.g. the user may issue a command
strobe, a register write and writing 3 bytes
to the TXFIFO in one operation, as
illustrated in Figure 11. The only exception
is that FIFO and RAM access must be
terminated by setting
CSn
high.
