CC2420
SWRS041B Page 80 of 89
TOPTST (0x2F) - Top Level Test Register
Bit
Field Name
Reset
R/W
Description
15:8 -
0
W0
Reserved, write as 0.
7 RAM_BIST_RUN
0
R/W
Enable BIST of the RAM
0 : RAM BIST disabled, normal operation
1 : RAM BIST Enabled. Result output to pin, as set in IOCFG1.
6 TEST_BATTMON_EN
0
R/W
Enable test output of the battery monitor.
5 VC_IN_TEST_EN
0
R/W
When ATESTMOD_MODE=7 this controls whether the ATEST2
in is used to output the VC node voltage (0) or to control the VC
node voltage (1).
4 ATESTMOD_PD
1
R/W
Powerdown of analog test module.
0 : Power up
1 : Power down
3:0
ATESTMOD_MODE[3:0] 0
When
ATESTMOD_PD
=0, the function of the analog test module
is as follows:
0: Outputs “I” (
ATEST1
) and “Q” (
ATEST2
) from RxMIX.
1: Inputs “I” (
ATEST2
) and “Q” (
ATEST1
) to BPF.
2: Outputs “I” (
ATEST1
) and “Q” (
ATEST2
) from VGA.
3: Inputs “I” (
ATEST2
) and “Q” (
ATEST1
) to ADC.
4: Outputs “I” (
ATEST1
) and “Q” (
ATEST2
) from LPF.
5: Inputs “I” (
ATEST2
) and “Q” (
ATEST1
) to TxMIX.
6: Outputs “P” (
ATEST1
) and “N” (
ATEST2
) from Prescaler. Must
be terminated externally.
7: Connects TX IF to RX IF and simultaneously the
ATEST1
pin
to the internal VC node (see
VC_IN_TEST_EN
).
8. Connect
ATEST1
(input) to
ATEST2
(output) through
single2diff and diff2single buffers, used for measurements on the
test-interface
RESERVED (0x30) - Reserved register containing spare control and status bits
Bit
Field Name
Reset
R/W
Description
15:0 RES[15:0]
0
R/W
Reserved for future use
TXFIFO (0x3E) – Transmit FIFO Byte register
Bit
Field Name
Reset
R/W
Description
7:0 TXFIFO[7:0]
0
W
Transmit FIFO byte register, write only. Reading the TXFIFO is
only possible using RAM read. Note that the crystal oscillator
must be running for writing to the TXFIFO.
RXFIFO (0x3F) – Receive FIFO Byte register
Bit
Field Name
Reset
R/W
Description
7:0 RXFIFO[7:0]
0
R/W
Receive FIFO byte register, read / write. Note that the crystal
oscillator must be running for accessing the RXFIFO.
