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User's Guide

SLAU250 – May 2008

1.5-GHz Low-Phase Noise Clock Evaluation Board

This user's guide discusses the general operation and configuration of the Texas Instruments CDCE72010
evaluation board.

Contents

1

Features

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2

2

General Description

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2

3

Signal Path and Control Circuitry

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3

4

Software Selectable Options

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3

5

Installing the GUI Interface and USB Driver

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3

6

CDCE72010 Control GUI Interface

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5

7

TI CDCE72010 Control GUI Interface

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5

7.1

Using Software-Enabled PLL Selection

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5

8

Configuring the Board

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10

8.1

Default Configuration for Programming and Testing With USB Cable Attached

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10

8.2

Configuration for Programming With USB Cable Attached

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10

8.3

Configuration for Testing From a Saved Configuration With USB Cable Removed After
Programming

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10

8.4

Configuration for Onboard External Loop Filter

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11

8.5

Configuration for PLL Lock Detect

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12

9

CDCE72010EVM Board Schematic Diagram

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13

List of Figures

1

CDCE72010EVM Board

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2

2

CDCE72010EVM External Loop Filter Topology

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12

Windows is a trademark of Microsoft Corporartion.

SLAU250 – May 2008

1.5-GHz Low-Phase Noise Clock Evaluation Board

1

Submit Documentation Feedback

Summary of Contents for CDCE72010

Page 1: ...led PLL Selection 5 8 Configuring the Board 10 8 1 Default Configuration for Programming and Testing With USB Cable Attached 10 8 2 Configuration for Programming With USB Cable Attached 10 8 3 Configu...

Page 2: ...puts and or the feedback path to the PFD The maximum VCXO VCO input frequency is 1 5 GHz It provides support for two redundant input references and using its on chip PLL architecture can provide up to...

Page 3: ...e 150 current setting resistors The LVCMOS outputs work for frequencies up to 250 MHz the LVDS outputs run up to 800 MHz and LVPECL outputs function up to 1 175 MHz these are all minimum frequencies T...

Page 4: ...r the driver location browse to the CDCE72010 GUI file folder that was used during instillation If the Windows operating system does not ask for a driver no action is required After the USB driver ins...

Page 5: ...Divider Input type Input selection PFD Charge Pump Output Divider and Output type The rest are selected by the software with user selectable options as described in the steps below If the power to th...

Page 6: ...he External Control Pins button in the EVM Status section of the GUI The selections on this popup window as shown in the following illustration must be selected according to the desired working config...

Page 7: ...to the CDCE72010 primary secondary inputs AC or DC termination input buffer internal termination enabled or disabled input buffer VBB voltage polarity normal or inverted input buffer hysteresis and f...

Page 8: ...lections on the charge pump current and charge pump pulse width Step 5 Output Divider The CDCE72010 has 10 outputs and 8 Output Dividers Outputs 0 and 1 share the same divider and outputs 8 and 9 shar...

Page 9: ...e separate CMOS outputs running at the same frequency Either CMOS output can be active inverting tri state or low Each output can be independently disabled Step 7 Write to CDCE72010 EEPROM To write an...

Page 10: ...its sole power source However due to power supply variances in the USB supply this configuration is not recommended for measurements This setup is for saving configuration settings to the CDCE72010 an...

Page 11: ...F and JP_3_6 and JP_3_7 for SEC_REF Each of these jumpers can be configured as shown in the following diagram for either LVPECL or LVDS bias If the CDCE72010 is chosen to be operated as a jitter clean...

Page 12: ...e Filter1 1 kHz Filter2 520 Hz Filter3 120 Hz and Filter4 15 Hz Figure 2 CDCE72010EVM External Loop Filter Topology The CDCE72010 PLL lock detect can be chosen on the CDCE72010EVM as either an analog...

Page 13: ...9 CDCE72010EVM Board Schematic Diagram www ti com CDCE72010EVM Board Schematic Diagram SLAU250 May 2008 1 5 GHz Low Phase Noise Clock Evaluation Board 13 Submit Documentation Feedback...

Page 14: ...CDCE72010EVM Board Schematic Diagram www ti com 1 5 GHz Low Phase Noise Clock Evaluation Board 14 SLAU250 May 2008 Submit Documentation Feedback...

Page 15: ...www ti com CDCE72010EVM Board Schematic Diagram SLAU250 May 2008 1 5 GHz Low Phase Noise Clock Evaluation Board 15 Submit Documentation Feedback...

Page 16: ...CDCE72010EVM Board Schematic Diagram www ti com 1 5 GHz Low Phase Noise Clock Evaluation Board 16 SLAU250 May 2008 Submit Documentation Feedback...

Page 17: ...www ti com CDCE72010EVM Board Schematic Diagram SLAU250 May 2008 1 5 GHz Low Phase Noise Clock Evaluation Board 17 Submit Documentation Feedback...

Page 18: ...CDCE72010EVM Board Schematic Diagram www ti com 18 1 5 GHz Low Phase Noise Clock Evaluation Board SLAU250 May 2008 Submit Documentation Feedback...

Page 19: ...duct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application enginee...

Page 20: ...siness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product wo...

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