Texas Instruments CDCE72010 User Manual Download Page 3

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Signal Path and Control Circuitry

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Software Selectable Options

5

Installing the GUI Interface and USB Driver

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Signal Path and Control Circuitry

The CDCE72010 provides support for selectable tri-inputs, and two of the inputs (PRI REF and SEC REF)
can accept a 8-kHz to 500-MHz frequency input from a differential signal source or a 8-kHz to 200-MHz
frequency input from a single-ended signal source.

The CDCE72010 provides support for up to ten differential (LVDS or LVPECL) or 20 single-ended
(LVCMOS) or any combination of outputs up to 1.5 GHz. On the CDCE72010EVM, output 1 and output 8
have a footprint option for installing crystal filters that can drive the phase noise floor down by 10 dB or 15
db. This filtered signal is intended to be used for clocking high-performance, high-speed analog-to-digital
converters (ADC).

The CDCE72010 requires an external loop filter. The loop filter selection determines the PLL loop stability
and also affects the phase noise of the output. The EVM provides four sets of filters optimized for a
30.72-MHz reference and 491.52-MHz VCXO. For any output of the CDCE72010, the frequency is
determined by the selection of the VCO/VCXO and the setting of the output divider. The output jitter
performance is determined by the PLL settings (including the PFD frequency, charge pump current, and
the loop filter). See the CDCE72010 data sheet for more details and configuration settings.

Each of the ten outputs of the CDCE72010 can be selected through the software interface as LVPECL,
LVDS, or LVCMOS. The CDCE72010EVM provides software selectable 150-

current-setting resistors.

The LVCMOS outputs work for frequencies up to 250 MHz; the LVDS outputs run up to 800 MHz; and
LVPECL outputs function up to 1.175 MHz (these are all minimum frequencies).

The provided GUI software allows users to easily send commands to the CDCE72010 through the
host-powered USB interface. The EVM includes a slave USB controller that transmits the commands to
the SPI programming interface included on the CDCE72010. The DC power for the USB controller can
either be derived from the 5-V power pin in the USB cable or by using an external 5-V DC adapter into the
slot available on the EVM. If the device is accessible for programming by the SPI programming interface
through the USB controller, the onboard LED D25 is illuminated on power up.

In addition to writing commands to the CDCE72010 RAM while the board is powered, commands also can
be stored in CDCE72010 EEPROM. This allows users to start the EVM in the desired state without
needing programming at power up.

Note that the CDCE72010 has a permanent EEPROM lock mode. After this mode is selected, the
EEPROM within the CDCE72010 cannot be changed. This is useful when setting final configurations.

The CDCE72010EVM software also provides support for the device GUI configurations to be saved into a
configuration file, which can be opened at a later time with this GUI.

To start installation, run the

CDCE72010 Control GUI v1.X.X.msi

file.

Make note of the installation folder because you may need to refer to it when the USB cable is connected
and asks for the location of a driver file.

After the setup wizard has completed, start the GUI interface from the start menu (Start

CDCE72010

Control GUI).

SLAU250 – May 2008

1.5-GHz Low-Phase Noise Clock Evaluation Board

3

Submit Documentation Feedback

Summary of Contents for CDCE72010

Page 1: ...led PLL Selection 5 8 Configuring the Board 10 8 1 Default Configuration for Programming and Testing With USB Cable Attached 10 8 2 Configuration for Programming With USB Cable Attached 10 8 3 Configu...

Page 2: ...puts and or the feedback path to the PFD The maximum VCXO VCO input frequency is 1 5 GHz It provides support for two redundant input references and using its on chip PLL architecture can provide up to...

Page 3: ...e 150 current setting resistors The LVCMOS outputs work for frequencies up to 250 MHz the LVDS outputs run up to 800 MHz and LVPECL outputs function up to 1 175 MHz these are all minimum frequencies T...

Page 4: ...r the driver location browse to the CDCE72010 GUI file folder that was used during instillation If the Windows operating system does not ask for a driver no action is required After the USB driver ins...

Page 5: ...Divider Input type Input selection PFD Charge Pump Output Divider and Output type The rest are selected by the software with user selectable options as described in the steps below If the power to th...

Page 6: ...he External Control Pins button in the EVM Status section of the GUI The selections on this popup window as shown in the following illustration must be selected according to the desired working config...

Page 7: ...to the CDCE72010 primary secondary inputs AC or DC termination input buffer internal termination enabled or disabled input buffer VBB voltage polarity normal or inverted input buffer hysteresis and f...

Page 8: ...lections on the charge pump current and charge pump pulse width Step 5 Output Divider The CDCE72010 has 10 outputs and 8 Output Dividers Outputs 0 and 1 share the same divider and outputs 8 and 9 shar...

Page 9: ...e separate CMOS outputs running at the same frequency Either CMOS output can be active inverting tri state or low Each output can be independently disabled Step 7 Write to CDCE72010 EEPROM To write an...

Page 10: ...its sole power source However due to power supply variances in the USB supply this configuration is not recommended for measurements This setup is for saving configuration settings to the CDCE72010 an...

Page 11: ...F and JP_3_6 and JP_3_7 for SEC_REF Each of these jumpers can be configured as shown in the following diagram for either LVPECL or LVDS bias If the CDCE72010 is chosen to be operated as a jitter clean...

Page 12: ...e Filter1 1 kHz Filter2 520 Hz Filter3 120 Hz and Filter4 15 Hz Figure 2 CDCE72010EVM External Loop Filter Topology The CDCE72010 PLL lock detect can be chosen on the CDCE72010EVM as either an analog...

Page 13: ...9 CDCE72010EVM Board Schematic Diagram www ti com CDCE72010EVM Board Schematic Diagram SLAU250 May 2008 1 5 GHz Low Phase Noise Clock Evaluation Board 13 Submit Documentation Feedback...

Page 14: ...CDCE72010EVM Board Schematic Diagram www ti com 1 5 GHz Low Phase Noise Clock Evaluation Board 14 SLAU250 May 2008 Submit Documentation Feedback...

Page 15: ...www ti com CDCE72010EVM Board Schematic Diagram SLAU250 May 2008 1 5 GHz Low Phase Noise Clock Evaluation Board 15 Submit Documentation Feedback...

Page 16: ...CDCE72010EVM Board Schematic Diagram www ti com 1 5 GHz Low Phase Noise Clock Evaluation Board 16 SLAU250 May 2008 Submit Documentation Feedback...

Page 17: ...www ti com CDCE72010EVM Board Schematic Diagram SLAU250 May 2008 1 5 GHz Low Phase Noise Clock Evaluation Board 17 Submit Documentation Feedback...

Page 18: ...CDCE72010EVM Board Schematic Diagram www ti com 18 1 5 GHz Low Phase Noise Clock Evaluation Board SLAU250 May 2008 Submit Documentation Feedback...

Page 19: ...duct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application enginee...

Page 20: ...siness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product wo...

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