8.4
Configuration for Onboard External Loop Filter
R2
C2
C1
C3
R3
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Configuring the Board
Configuration for Onboard Reference Input Biasing.
If the on-chip biasing is not used in the
CDCE72010 for AC-coupled reference input signals for PRI_REF or SEC_REF, the CDCE72010EVM
alternately can be set up to provide onboard biasing for LVPECL or LVDS inputs. These bias voltages of
1.2 V for LVDS and 1.9 V for LVPECL are derived from the onboard voltage divider. The bias points are
available for every leg of the differential signals at both PRI_REF and SEC_REF and can be enabled by
using the jumpers on the CDCE72010EVM, JP_3_4 and JP_3_5 for PRI_REF and JP_3_6 and JP_3_7
for SEC_REF. Each of these jumpers can be configured as shown in the following diagram for either
LVPECL or LVDS bias.
If the CDCE72010 is chosen to be operated as a jitter cleaner, it requires use of the partially external loop
filter which is located at the back side of the CDCE72010EVM. The EVM provides four external loop filter
options. The external loop filter topology is shown in the following diagram. The device can handle more
complex filter topologies, including active loop filters, but the EVM is only designed to illustrate
second-order filter topology. Remember that the loop filter is calculated for and operates with a particular
PFD frequency, charge pump current, and PLL gain (determined by the feedback divider settings).
SLAU250 – May 2008
1.5-GHz Low-Phase Noise Clock Evaluation Board
11