Texas Instruments CDC7005, User Manual, Page: 18 / 37

Hardware Configuration
3-6
The reference input clock signal has to be applied to J19. The reference input
clock signal can be sensed on J20. In this case, close the bridge J36 (the
oscilloscope’s 50
Ω may be used to terminate the 50- Ω trace). The reference
input clock sense line is matched to the LVPECL outputs line to avoid any
additional delay offset. The input is ac-coupled (C57) and properly biased with
100-
Ω pull-up and 100- Ω pull-down resistors.
3.3.6 VCXO Inputs and Outputs (J23 − J28)
The CDC7005 requires an external VCXO in order to complete the PLL loop.
The VCXO adjusts the frequency and phase depending on the control voltage
level coming from loop filter and provide the input clock to the LVPECL block.
The circuitry lets the user:
-
Measure the on-board VCXO output from outside on J23 and J24 (close
1
− 3 of J21 and 1 − 3 of J22).
-
Feed the LVPECL clock from an external source into the VCXO_IN/
VCXO_INB inputs of the CDC7005. If the CDC7005 is intended to be used
as a programmable clock buffer without PLL capabilities, then close 2
− 3
of J21 and J22. In case of using an external oscillator (or VCXO), close 2 − 3
of J21 and J22. The VCXO output clock has to be applied on J23 and J24
and VCXO control voltage can be taken on TP1.
Default settings: J17 is open, 1 − 2 of J21 and J22 are connected.
Note:
This EVM offers universal foot print for VCXO, so it allows the addition of
several VCXO’s.