Texas Instruments CDC7005, User Manual, Page: 16 / 37

Hardware Configuration
3-4
3.3.1 Power Supply (P1, P2)
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Supply 3.3 V ± 10% on P1 and P2 using a stabilized external power supply.
J
WARNING: Never supply more than 3.6 V on P1.
3.3.2 Onboard Switches and Indicators (P1, P2, D1 − D4)
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Push SW1 to enter the power-down mode of the CDC7005 device. Then
all current sources are switched off, all outputs are switched into 3-state,
and all dividers (M, N, and P) are reset to default.
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Push SW2 to enter the reset mode of the device. Then the dividers (M, N,
and P) are reset to default.
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The three status outputs of the CDC7005 are fed to LED indicators and
to pin header J5. An D1 on condition indicates a valid reference input clock
signal, D2 is on if the VCXO input clock is valid, and D3 turns on if PLL has
been locked.
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D4 indicates power supply
Default setting: I_REF is connected to ground through a 12-k Ω resistor . For
default operation, the device uses an internal resistor.
Note:
In case of low input impedance of the VCXO control voltage input, there is
a possibility D3 may not turn on to indicate locking.
3.3.3 Programming Interfaces (J27, J28)
The SPI of the device is used for writing to the control register of the device.
It consists of three control lines CTRL_CLK, CTRL_DATA, and CTRL_LE.
There are four 30-bit wide RAM registers, which can be addressed by the two
LSBs of a transferred word. Every transmitted word must have 32 bits, starting
with MSB. After supplying power or activating the power-down mode, the
registers are loaded with the device default values internally (see the
CDC7005 data sheet, SCAS685). However, if specific register settings are
required for any applications, there are two ways to program the device
externally:
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Connect the parallel port cable to the PC and EVM parallel port. This
needs control S/W (see Chapter 5).
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Connecting an external pattern generator to J28. Connect pin 18 of J27
to the ground.