8.5 Electrical Characteristics (continued)
(UVLO)
< V
IN
< V
(OVP)
and V
IN
> V
(BAT)
+ V
(SLP)
, T
J
= –40°C to 85°C and T
J
= 25°C for typical values
(unless otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
(DSCH_LSLDO)
MOSFET on-resistance
for LS/LDO discharge
1.7 V < V
(VINLS)
< 6.6 V, I
LOAD
= –10 mA
20
Ω
I
(OCL_LDO)
Output Current Limit –
LDO
V
LS/LDO
= 0 V
275
365
475
mA
I
(LS/LDO)
Output Current
V
(VINLS)
= 3.6 V, V
LSLDO
= 3.3 V
100
mA
V
(VINLS)
= 3.3 V, V
LSLDO
= 0.8 V
100
mA
V
(VINLS)
= 2.2 V, V
LSLDO
= 0.8 V
10
mA
I
IN(LDO)
Quiescent current for
VINLS in LDO mode
0.9
µA
OFF-state supply current
0.25
µA
V
IH(LSCTRL)
High-level input voltage
for LSCTRL
1.15 V > V
(VINLS)
> 6.6 V
0.75 x
V
(SYS)
6.6
V
V
IL(LSCTRL)
Low-level input voltage
for LSCTRL
1.15 V > V
(VINLS)
> 6.6 V
0.25 x
V
(SYS)
V
PUSHBUTTON TIMER ( MR)
V
IL
Low-level input voltage
V
BAT
> V
BUVLO
0.3
V
R
PU
Internal pull-up
resistance
120
kΩ
VBAT MONITOR
V
BMON
Battery Voltage Monitor
Accuracy
V
(BAT)
Falling - Including 2% increment
–3.5
3.5 %V
(BATREG)
BATTERY-PACK NTC MONITOR
V
HOT
High temperature
threshold
V
TS
falling, 1% V
IN
Hysteresis
14.5
15
15.2
%V
IN
V
WARM
Warm temperature
threshold
V
TS
falling, 1% V
IN
Hysteresis
20.1
20.5
20.8
%V
IN
V
COOL
Cool temperature
threshold
V
TS
rising, 1% V
IN
Hysteresis
35.4
36
36.4
%V
IN
V
COLD
Low temperature
threshold
V
TS
rising, 1% V
IN
Hysteresis
39.3
39.8
40.2
%V
IN
TS
OFF
TS Disable threshold
V
TS
rising, 2% V
IN
Hysteresis
55
60
%V
IN
PROTECTION
V
(UVLO)
IC active threshold
voltage
V
IN
rising
3.4
3.6
3.8
V
V
UVLO(HYS)
IC active hysteresis
V
IN
falling from above V
UVLO
150
mV
V
(BUVLO)
Battery Undervoltage
Lockout threshold Range
Programmable Range for V
(BUVLO)
VBAT falling, 150 mV
Hysteresis
2.2
3.0
V
Default Battery
Undervoltage Lockout
Accuracy
V
(BAT)
falling
–2.5%
2.5%
V
(BATSHORT)
Battery short circuit
threshold
Battery voltage falling
2
V
V
(BATSHORT_HYS)
Hysteresis for
V
(BATSHORT)
100
mV
I
(BATSHORT)
Battery short circuit
charge current
I
(PRETERM)
mA
V
(SLP)
Sleep entry threshold, V
IN
– V
(BAT)
2 V < V
BAT
< V
(BATREG)
, V
IN
falling
65
120
mV
V
(SLP_HYS)
Sleep-mode exit
hysteresis
V
IN
rising above V
(SLP)
40
65
100
mV
V
OVP
Maximum Input Supply
OVP threshold voltage
V
IN
rising, 100 mV hysteresis
5.35
5.55
5.75
V
t
DGL_OVP
Deglitch time, VIN OVP
falling
V
IN
falling below V
OVP
, 1V/us
32
ms
T
SHTDWN
Thermal trip
V
IN
> V
UVLO
114
°C
SLUSDA7A – APRIL 2018 – REVISED JANUARY 2021
10
Copyright © 2021 Texas Instruments Incorporated
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