8.5 Electrical Characteristics (continued)
(UVLO)
< V
IN
< V
(OVP)
and V
IN
> V
(BAT)
+ V
(SLP)
, T
J
= –40°C to 85°C and T
J
= 25°C for typical values
(unless otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
T
HYS
Thermal hysteresis
V
IN
> V
UVLO
11
°C
t
DGL_SHTDWN
Deglitch time, Thermal
shutdown
T
J
rising above T
SHTDWN
4
µs
I2C INTERFACE
I
2
C Bus Specification
standard and fast mode
frequency support
100
400
kHz
V
IL
Input low threshold level
V
PULLUP
= 1.1 V, SDA and SCL
0.275
V
V
IH
Input high threshold level V
PULLUP
= 1.1 V, SDA and SCL
0.825
V
V
IH
Input high threshold level V
PULLUP
= 3.3 V, SDA and SCL
2.475
V
V
OL
Output low threshold
level
IL = 5 mA, sink current, V
PULLUP
= 1.1 V
0.275
V
I
BIAS
High-Level leakage
current
V
PULLUP
= 1.8 V, SDA and SCL
1
µA
INT, PG, and RESET OUTPUT (Open Drain)
V
OL
Low level output
threshold
Sinking current = 5 mA
0.25 x
V
(SYS)
V
I
IN
Bias current into pin
Pin is high impedance, I
OUT
= 0 mA; T
J
= –40°C to 60°C
12
nA
V
IN(BAT_DELTA)
Input voltage above
VBAT where PG sends
two 128 µs pulses each
minute to signal the host
of the input voltage status
V
UVLO
< V
IN
< V
OVP
0.825
1
1.15
V
INPUT PIN ( CD LSCTRL)
V
IL(/CD_LSCTRL)
Input low threshold
V
(PULLUP)
= V
SYS
= 3.3 V
0.25 * V
SYS
V
V
IH(/CD_LSCTRL)
Input high threshold
V
(PULLUP)
= V
SYS
= 3.3 V
0.75 * V
SYS
V
R
PULLDOWN/CD
Internal pull-down
resistance
900
kΩ
R
(LSCTRL)
Internal pull-down
resistance
2
MΩ
SLUSDA7A – APRIL 2018 – REVISED JANUARY 2021
Copyright © 2021 Texas Instruments Incorporated
11
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