9.6.3 TS Control and Faults Masks Register
Memory location 0x02h, Reset State: 1xxx 1000 (BQ25121A)
Figure 9-13. TS Control and Faults Masks Register (02)
7 (MSB)
6
5
4
3
2
1
0 (LSB)
1
x
x
x
1
0
0
0
R/W
R
R
R
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-14. TS Control and Faults Masks Register, Memory Location 0010
Bit
Field
Type
Reset
Description
B7 (MSB) TS_EN
R/W
1
0 – TS function disabled
1 – TS function enabled
B6
TS_FAULT1
R
x
TS Fault mode:
00 – Normal, No TS fault
01 – TS temp < T
COLD
or TS temp > T
HOT
(Charging suspended)
10 – T
COOL
> TS temp > T
COLD
(Charging current reduced by
half)
11 – T
WARM
< TS temp < T
HOT
(Charging voltage reduced by
140 mV)
B5
TS_FAULT0
R
x
B4
Reserved
R
x
Reserved
B3
EN_INT
R/W
1
0 – Disable INT function (INT only shows faults and does not
show charge status)
1 – Enable INT function (INT shows faults and charge status)
B2
WAKE_M
R/W
0
1 – Mask interrupt from Wake Condition from MR
B1
RESET_M
R/W
0
1 – Mask RESET interrupt from MR . The RESET output is not
masked by this bit.
B0 (LSB) TIMER_M
R/W
0
1 – Mask Timer fault interrupt (safety)
To save power, the device will shut off the clock that counts the deglitch time for the faults in the Hi-Z mode. For any of the fault conditions
that contain a deglitch time as specified in the
, the device will have to be in Active BAT with an I
2
C transaction or VIN present to
count against the deglitch to clear the fault on the register.
SLUSDA7A – APRIL 2018 – REVISED JANUARY 2021
Copyright © 2021 Texas Instruments Incorporated
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