background image

BQ2415x

EVM

DC+

J 1

DC -

BAT+

S

C

L

BAT -

APPLICATION

CIRCUIT

U1

J3

J5

J 4

J2

D1

JMP1

JMP2

JMP3

AUXPWR

CD

S

D

A

D

C

-

D

C

-

S

T

A

T

O

T

G

S

L

R

S

T

JMP5

JMP4

V

I

Power

supply #1

Load

#1

Io

I

I in

USB
Cable

HPA172

Ribbon
Cable

V

Printed-Circuit Board Layout Guideline

www.ti.com

Figure 4. Boost Function Test Setup

3. Turn on PS#1 output.

4. Software setup: Change Operation Mode to Boost Mode.

Measure

V(J1(DC+, DC–)) = 5 V ±0.2 V

5. Enable Load #1.

Measure

V(J1(DC+, DC–)) = 5 V ±0.2 V

Measure

Iin = 330 mA ±40 mA

Measure

Io = 200 mA ±20 mA

3

Printed-Circuit Board Layout Guideline

1. To obtain optimal performance, the power input capacitors, connected from input to PGND, must be

placed as close as possible to the integrated circuit (IC).

2. The output inductor must be placed close to the IC and the output capacitor connected between the

inductor and PGND of the IC. The intent is to minimize the current path loop area from the SW pin
through the LC filter and back to the PGND pin. To prevent high-frequency oscillation problems, proper
layout to minimize high-frequency current path loop is critical.

3. The sense resistor must be adjacent to the junction of the inductor and output capacitor. Route the

sense leads connected across the RSNS back to the IC, close to each other (minimize loop area) or
on top of each other on adjacent layers (do not route the sense leads through a high-current path).

4. Place all decoupling capacitors close to their respective IC pin and as close as to PGND (do not place

components such that routing interrupts power stage currents). All small control signals must be routed
away from the high current paths.

5. The PCB must have a ground plane (return) connected directly to the return of all components through

vias (two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per
capacitor for small-signal components). A star ground design approach is typically used to keep circuit
block currents isolated (high-power/low-power small-signal) which reduces noise-coupling and ground-
bounce issues. A single ground plane for this design gives good results. No ground-bounce issue
occurs with this small layout and a single ground plane. Having the components segregated minimizes
coupling between signals.

6. The high-current charge paths into VBUS, PMID, and from the SW pins must be sized appropriately for

the maximum charge current in order to avoid voltage drops in these traces. The PGND pins must be
connected to the ground plane to return current through the internal low-side FET.

8

bq24153A/56A/57/58/59 Fully Integrated, Switch-Mode, One-Cell, Li-Ion

SLUU453C – November 2010 – Revised May 2013

Charger With Full USB Compliance and USB-OTG Support EVM

Submit Documentation Feedback

Copyright © 2010–2013, Texas Instruments Incorporated

Summary of Contents for bq24153A

Page 1: ...ary 3 2 1 Definitions 3 2 2 Recommended Test Equipment 3 2 3 Recommended Test Equipment Setup 4 2 4 Recommended Test Procedure 6 3 Printed Circuit Board Layout Guideline 8 4 Bill of Materials Board Layout and Schematics 9 4 1 Bill of Materials 9 4 2 Board Layout 10 4 3 Schematic 12 List of Figures 1 Connections of HPA172 Kit 4 2 Charging Function Test Setup 5 3 Main Window of bq24153A_9 Evaluation...

Page 2: ...interface For details see the bq24153A 56A 58 59 data sheet SLUSAB0 and the bq24157 datasheet SLUSAX5 1 3 I O Description Jack Description J1 DC AC adapter or USB positive output J1 DC AC adapter or USB negative output J2 BAT Battery negative terminal connect to DC J2 AUXPWR CD Connect to AUXPWR pin or CD pin J2 BAT Charger positive output connect to CSOUT pin J3 SCL I2 C clock connect to SCL pin ...

Page 3: ...est point which is marked as ACDET V XXX YYY Voltage across point XXX and YYY I JXX YYY Current going out from the YYY terminal of jack XX Jxx BBB Terminal or pin BBB of jack xx Jxx ON Internal jumper Jxx terminals are shorted Jxx OFF Internal jumper Jxx terminals are open Jxx YY ON Internal jumper Jxx adjacent terminals marked as YY are shorted Measure A B Check specified parameters A B If measur...

Page 4: ... of Power Supply 1 in series with a current meter multimeter to J1 DC DC 3 Connect a voltage meter across J1 DC DC 4 Connect the Load 2 in series with a current meter multimeter to J2 BAT BAT Ensure that a voltage meter is connected across J2 BAT BAT Turn on the Load 2 Use the constant voltage mode Set the output voltage to 2 5 V 5 Turn off Load 2 6 Connect J5 to HPA172 kit by the 10 pin ribbon ca...

Page 5: ...LO ON ON bq24157 HPA256 003 LED ON HI ON OFF LO ON ON bq24159 8 After the preceding steps the test setup for HPA697 is shown in Figure 2 Figure 2 Charging Function Test Setup 9 Turn on the computer Open the bq24153A_9 evaluation software Select part number and click the GO button The main window of the software is shown in Figure 3 5 SLUU453C November 2010 Revised May 2013 bq24153A 56A 57 58 59 Fu...

Page 6: ...4156A and bq24159 only is logic high In addition on the bq24156A and bq24159 the Safety Limit Register bits are reset to default values and can be changed immediately after the SLRST pin transitions from logic low to logic high if V CSOUT is above VSHORT 2 05V typ Once a change WRITE command to any other register is made the safety limit registers are locked until one of the previously explained t...

Page 7: ...dic Reads and set Rate to 5 seconds Ensure that Rsense is set to 68 mΩ Ensure that Operation Mode is Charger Mode except for bq24156A and bq24159 Uncheck Charge Current Termination if checked Check STAT Pin Select Charge Current Sense Voltage to Normal 5 Change Charge Current to 950mA and change Input Current Limit to 500mA Measure Ichrg 650 mA 850mA Measure Iin 440mA 500mA Observe Diode D1 is on ...

Page 8: ... other on adjacent layers do not route the sense leads through a high current path 4 Place all decoupling capacitors close to their respective IC pin and as close as to PGND do not place components such that routing interrupts power stage currents All small control signals must be routed away from the high current paths 5 The PCB must have a ground plane return connected directly to the return of ...

Page 9: ...ing 0 100 inch x 2 PEC02SAAN Sullins 0 1 0 0 1 L1 1 µH 2 5mmx2mm 1 0uH 30 1 6A 0 11x0 09 inch LQM2HPN1R0MJ0 or CP1008 Murata or Inter Technical 1 0 1 1 0 L1 1 µH 2 5mmx2mm 1 0uH 30 1 3A 0 11x0 09 inch LQM2HPN1R0MJ0 or MDT2520 Murata or TOKO or CN1R0M or CP1008 Inter Technical 1 1 1 1 1 R1 0 068 Resistor Chip 125mW 5 0402 ERJ 2BWJR068X Panasonic 1 1 1 1 1 R2 5 1k Resistor Chip 1 16 W 5 0603 Std Std...

Page 10: ...Q24158EVM 697 HPA697 004 BQ24157EVM 697 HPA697 005 BQ24159EVM 697 4 2 Board Layout Figure 5 Top Layer 10 bq24153A 56A 57 58 59 Fully Integrated Switch Mode One Cell Li Ion SLUU453C November 2010 Revised May 2013 Charger With Full USB Compliance and USB OTG Support EVM Submit Documentation Feedback Copyright 2010 2013 Texas Instruments Incorporated ...

Page 11: ...Layer Figure 7 Top Assembly 11 SLUU453C November 2010 Revised May 2013 bq24153A 56A 57 58 59 Fully Integrated Switch Mode One Cell Li Ion Charger With Full USB Compliance and USB OTG Support EVM Submit Documentation Feedback Copyright 2010 2013 Texas Instruments Incorporated ...

Page 12: ...com 4 3 Schematic 12 bq24153A 56A 57 58 59 Fully Integrated Switch Mode One Cell Li Ion SLUU453C November 2010 Revised May 2013 Charger With Full USB Compliance and USB OTG Support EVM Submit Documentation Feedback Copyright 2010 2013 Texas Instruments Incorporated ...

Page 13: ...WARE section 4 Added Factory Jumper Settings 4 Changed Original Test Setup for HPA256 bq2415x EVM 5 Updated lit item 9 5 Added New figure 6 7 Changed title 7 Removed bq24157B from the schematic 12 NOTE Page numbers for previous revisions may differ from page numbers in the current version Revision History Changes from Original November 2010 to A Revision Page Changed the Maximum Charge Current and...

Page 14: ...ndling and use of EVMs and if applicable compliance in all respects with such laws and regulations 10 User has sole responsibility to ensure the safety of any activities to be conducted by it and its employees affiliates contractors or designees with respect to handling and using EVMs Further user is responsible to ensure that any interfaces electronic and or mechanical between EVMs and any human ...

Page 15: ...This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at its own expense FCC Interference Statement ...

Page 16: ...érieur au gain maximal indiqué sont strictement interdits pour l exploitation de l émetteur Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2014 Texas Instruments Incorporated spacer Important Notice for Users of EVMs Considered Radio Frequency Products in Japan EVMs entering Japan are NOT certified by TI as conforming to Technical Regulations of Radio Law of ...

Page 17: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

Page 18: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments BQ24157EVM 697 ...

Reviews: