Texas Instruments AN-2166 LMZ10500, Manual

Page: 19 / 28

INPUT
CAPACITOR
OUTPUT
CAPACITOR
FEEDBACK
TRACE
VIN
VOUT
VCON
CAPACITOR
VREF
VIN
PGND
VOUT SGND
FB
SGND CONNECTION TO
QUIET PGND PLANE
VCON
EN
RT
RESISTOR
RB
RESISTOR
HIGH di/dt LOOP
KEEP IT SMALL
PGND
LMZ10500
www.ti.com SNVS723C – OCTOBER 2011 – REVISED MARCH 2013
Board Layout Considerations
Figure 39. Example Top Layer Board Layout
The board layout of any DC-DC switching converter is critical for the optimal performance of the design. Bad
PCB layout design can disrupt the operation of an otherwise good schematic design. Even if the regulator still
converts the voltage properly, the board layout can mean the difference between passing or failing EMI
regulations. In a Buck converter, the most critical board layout path is between the input capacitor ground
terminal and the synchronous rectifier ground. The loop formed by the input capacitor and the power FETs is a
path for the high di/dt switching current during each switching period. This loop should always be kept as short
as possible when laying out a board for any Buck converter.
The LMZ10500 integrates the inductor and simplifies the DC-DC converter board layout. Refer to the example
layout in
Figure 39 . There are a few basic requirements to achieve a good LMZ10500 layout.
1. Place the input capacitor C
IN
as close as possible to the V
IN
and PGND terminals. V
IN
(pin 7) and PGND
(pin 6) on the LMZ10500 are next to each other which makes the input capacitor placement simple.
2. Place the V
CON
filter capacitor C
VC
and the R
B
R
T
resistive divider as close as possible to the V
CON
and
SGND terminals.The C
VC
capacitor (not R
B
) should be the component closer to the V
CON
pin, as shown in
Figure 39 . This allows for better bypass of the control voltage set at V
CON
.
3. Run the feedback trace (from V
OUT
to FB) away from noise sources.
4. Connect SGND to a quiet GND plane.
5. Provide enough PCB area for proper heatsinking. Refer to the Electrical Characteristics table for example
θ
JA
values for different board areas. Also, refer to AN-2020 for additional thermal design hints.
Refer to the evaluation board application note AN-2166 for a complete board layout example.
Copyright © 2011–2013, Texas Instruments Incorporated
Submit Documentation Feedback 19
Product Folder Links: LMZ10500