D21
D24
R20
C12
R21
COMP
LM3450A
BIAS
V
ADJ
V
CC
Q4
D20
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Design Information
•
P
OUT-MAX
and C11 are exactly directly proportional given a constant output ripple specification, therefore
there is no relative change to
ω
P1
.
•
V
OUT
is exactly inversely proportional to
ω
P1
given a constant output ripple specification.
With the opposing conditions of the output pole moving inversely proportional to V
OUT
and the DC gain
moving proportional to V
OUT
, the net result gives a very consistent uncompensated loop gain. Because of
this, the exact compensator on this evaluation board can be a starting point for any LM3450A design.
During prototyping, If stability becomes a concern, the R77 value can be changed to improve stability. In
general the compensator calculated in the Design Calculations section is sized to be stable and have a
bandwidth of around 50-60Hz. This is a fairly high bandwidth for a PFC converter which will cause there to
be some 120Hz ripple on COMP. This will decrease PF but improve transient response which is very
helpful in phase dimmable applications.
Since it is usually desirable to maximize bandwidth (within the PFC limitation), there is a simple method to
adjust the R77 value. Measure the twice-line frequency ripple on COMP. If the ripple is less than 200-
300mV, increase R77 until it is within that range. If the ripple is larger, then decrease R77 until it is within
that range. This will result in a very small PFC degradation, while maximizing bandwidth of the control
loop.
9.9
STARTUP
When using the LM3450A with a phase dimmer, startup can be very disruptive. Any time the dimmer is
turned on (via a separate switch or some state where the dimmer has been previously disconnected from
its load), the LM3450A will attempt to bring the system to regulation. Because phase dimmers can be
turned on and off quickly, the system capacitances may or may not be fully discharged, this can lead to a
large variance in startup conditions. The best way to control startup transients is to softstart the dimming
command and the PFC control simultaneously. This can be accomplished with the circuit shown in
Figure 20
. D20 is a dual common cathode schottky with very low forward voltage to allow COMP and
VADJ to be pulled as close to zero as possible. The softstart time constant is set by C12 and R20. Q4,
R21, and D21 form a reset circuit for C12. Since BIAS transitions to 20V whenever VCC hits the falling
UVLO threshold and D21 is an 18V Zener, the base of Q4 will go high turning on Q4 and immediately
resetting the capacitor to 0V. Then when VCC reaches the UVLO rising threshold and BIAS transitions to
14V, Q4 turns off and softstart is active again.
Figure 20. Primary Soft-start Circuit
Relevant Definitions
G
VC
(s) – Converter Control-to-Output Transfer Function
G
C0
– Converter Control-to-Output DC Gain
G
3450
– LM3450A and External Gains
G
COMP
(s) – Compensator Transfer Function
H
FB
– Feedback Gain
ω
P1
– Converter Output Pole
ω
P2
– Compensator Secondary Integrator Pole
21
SNVA485B – June 2011 – Revised May 2013
AN-2150 LM3450A Evaluation Board
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