Texas Instruments AFE5818, User Manual

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EVM Headers, Test Points, and Configuration
33 SLOU430A – December 2015 – Revised February 2016
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Hardware Configuration
Table 2. EVM Rev.C Testpoints (continued)
Testpoint Circuit Label Testpoint Description
TP51 DTGC TGC_SLP Ext TGC_Slope
TP35 DTGC TGC_UD Ext TGC_Up/Down
TP40,41 LMK Clock Circuit CP1,CP2 LMK Output CP1,CP2
TP42 LMK Clock Circuit CLK_GTXP LMK GTX CLK to FPGA P
TP43 LMK Clock Circuit FPGA_SYSREF
P LMK SYSREF CLK to FPGA P
TP44,46 LMK Clock Circuit None LMK ADC Clock to Dut P/N
TP45,47 LMK Clock Circuit None LMK SYSREF Clock to Dut P/N
TP48 LMK Clock Circuit FPGA_CLK_OUT
_P LMK ADC CLK to FPGA P
TP49 LMK Clock Circuit None LMK VCXO output
B.1.3 ADC Clock Source Configuration
The AFE clock input can be driven differentially (sine wave, LVPECL, or LVDS) or single-ended
(LVCMOS). The clock input of the device has an internal buffer and clock amplifier which is enabled or
disabled automatically, depending on the type of clock provided (auto detect feature). Therefore, the EVM
allows for two options of clock input for LVDS mode (S-E and Differential), and two options of clock input
for JESD204B mode (Differential).
Figure 49. EVM ADC Clock Source Configuration