1
3
2
4
8
OPA2320AIDGKR
U10A
7
5
6
4
8
OPA2320AIDGKR
U10B
AGND
100nF
C25
OPA_VDD
OPA_VDD
0
R45
DNP
AGND
AVDD/4
VBIAS
AINM
AVDD/2
Figure 2-6. Buffer Amplifier Circuit on the ADS704X-5XEVM
The buffer amplifier in
prevents the AVDD/4 resistor divider (R3 and R5) from loading the amplifier
inputs and the AVDD/2 resistor divider (R7 and R9) from loading the ADC inputs (see
, VBIAS sets the driver amplifier common-mode voltage for both signal paths. AINM is only required if U3 or
is populated with the ADS7043. This specific ADC has a pseudo-differential input that requires
the AINM pin to be set to AVDD / 2 ±100 mV.
When the ADS7043 is used on the ADS704X-5XEVM:
• Depopulate R40 in
2.3 Digital Interface and Communication
The EVM interfaces with the PHI and communicates with the computer over the USB. There are three devices
on the EVM with which the PHI communicates: the two ADCs (over SPI) and the EEPROM (over I
2
C). The
EEPROM comes preprogrammed with the information required to configure and initialize each ADC populated
by default on the ADS704X-5XEVM. Therefore, communication with the EEPROM is only required if the user
removes and replaces one of the default ADCs. See
for more information.
All ADCs supported by the ADS704X-5XEVM use SPI serial communication in mode 1 (CPOL = 0, CPHA
= 1). The ADS704X-5XEVM offers 49.9-Ω resistors between the SPI signals to aid with signal integrity (see
) because the serial clock (SCLK) frequency can be as fast as 60 MHz. Typically, in high-speed SPI
communication, fast signal edges can cause overshoot; these 49.9-Ω resistors slow down the signal edges to
minimize signal overshoot. JP5 provides test points to measure the digital signals, as illustrated in
Introduction to the ADS704X-5XEVM
8
ADS7042EVM-PDK, ADS7049-Q1EVM-PDK, and ADS7057EVM-PDK
Evaluation Module
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