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Circuit Description
2.1
Schematic Diagram
2.2
ADC Circuit Function
2.2.1
ADC Operational Mode
2.2.2
ADC Power
2.2.3
ADC Analog Inputs
Circuit Description
The schematic diagram for the EVM is in
Section 4.3
.
The following sections describe the function of individual circuits. Refer to the relevant data sheet for
device operating characteristics.
By default, the ADC is configured to operate in parallel-mode operation, because the surface-mount
jumper asserts a 3.3-V state to the ADC reset pin. Consequenty, the SW1 reset pushbutton must be
pressed only when the device is configured into serial operational mode. Because the ADC is in parallel
operation mode, voltages are used to set the ADC modes. Users can use the EVM silkscreen to set the
operation modes.
Power is supplied to the EVM via banana jack sockets. Separate connections are provided for a 3.3-V
digital buffer supply (P1) and 3.3-V analog supply (P3). In most cases, these can be shorted together for
ADC evaluation. When using the amplifier evaluation path, users must connect the positive rail to J21 and
the negative rail to J22. The voltages depend on the coupling method and connection to the ADC. If the
ADC VCM is not supplied to the amplifier and the amplifier is connected to the ADC in a dc-coupled
fashion, users should set J21 to 4 V and J22 to –1 V. In ac-coupled configurations where the ADC VCM
biases the ADC inputs, users can connect J21 to 5 V and J22 to GND.
The EVM is configured to accept a single-ended input souce and convert it to an ac-coupled differential
signal using a transformer. The inputs to the ADC must be dc-biased, which is accomplished by using the
ADC VCM output. The inputs are provided via SMA connectors J10 for ADC channel A, J11 for ADC
channel B, J13 for ADC channel C, and J14 for ADC channel D. ADC input channel C also includes the
option for ADC evaluation using an amplifier signal chain.
TI has tested this ADC with a variety of transformer brands, transorfmer configurations and terminations.
For many applications, a single low-cost transformer can be used in the input signal chain to a very high
degree of performance. Customers should select a transformer configuration based on their ADC input
bandwidth frequency. To assist in this process, TI has swept the analog input frequency and plotted the
resulting ADC SFDR performance with various transformers.
Figure 1
and
Figure 2
show the ADC
performance using the Mini-Circuits TC1-1T, Mini-Circuits TC4-1W, and Coilcraft WBC1-1TLB in one- and
two-tranformer configurations, respectively. In both plots, the results were taken on an ADS6443, sampling
at 80 MSPS and on the same input channel. The termination was changed according to the impedance
ratio of the transfomer used.
Using SMA input J2, users can evaluate the ADC using a THS4509 amplifier, which converts a
single-ended input into a differential signal while providing 10 dB of signal gain. Users should enable the
amplifier path by connecting JP6 1–2 and by shorting positions 1–2 on both surface-mount jumpers JP1
and JP2. At low input frequencies, the ADC represents a high input impedance and R10, R19, and C45
form a low-pass filter with a 3-db cutoff frequency of 70 MHz. Users should change these component
values depending on the bandwidth of the signal they are digitizing to band-limit the input noise into the
ADC. Using an excessively high cutoff frequency degrades the SNR of the system. Before users begin
evaluation of the amplifier path, one most choose whether to dc-couple or ac-couple to the amplifier path.
In a dc-coupled system, users should replace C46 and C47 with 0-
Ω
resistors and remove R9 and R18.
The ADC VCM should be used to set the CM input of the amplifier by making sure R84 is populated with a
0-
Ω
resistor. Because the ADC has a common-mode voltage of 1.5 V, and because the THS4509 is not a
rail-to-rail amplifier, users should adjust VCC to 4 V and –VCC to –1 V, which can be done by applying the
respective voltages to J21 and J22.
SLAU196 – April 2007
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