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ADS64XX EVM.
6. ADS64XX and TSW1200: Switch power supplies on.
7. ADS64XX: Using a low-phase-noise, filtered frequency generator with 50-
Ω
source output impedance,
generate a 0-V offset, 1.5-Vrms sine-wave clock into J12. The frequency of the clock must be within
the specification for the device speed grade. TI uses an Agilent 8644B with a crystal MCF filter as a
clock source.
8. TSW1200: Depress SW4 (FPGA reset). This resets the logic inside the FPGA and must be done every
time one changes the ADC clock frequency.
9. ADS64XX: Using a low-phase-noise, filtered frequency generator with a 50-
Ω
source output
impedance, generate a 10-MHz, 0-V offset, –1-dBFS-amplitude sine-wave signal into either J10 (input
channel A) or J11 (input channel B). This provides a transformer-coupled differential input signal to the
ADC. TI uses an Agilent 8644B with an LC filter as a signal source.
10. TSW1200: The deserialized parallel output data can be probed using a logic analyzer on J5 for inputs
to ADC channel A and on J4 for inputs to ADC channel B. On both output headers, the clock can be
found on the respective output header on pin 2, and the LSB can be found on pin 6.
Note:
Any time the clock frequency of the ADC changes during the ADC evaluation, one must reset
the FPGA deserializer by depressing SW4. This allows the deserializer to re-align the ADC
data capture to the new output clock frequency.
6
SLAU196 – April 2007
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