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DA0_M
DA0_P
DA1_M
DA1_P
DB0_M
DB0_P
DB1_M
DB1_P
DCLK_M
DCLK_P
FCLK_M
FCLK_P
DC0_M
DC0_P
DC1_M
DC1_P
DD0_M
DD0_P
DD1_M
DD1_P
FPGA_PDN
FPGA_SCLK
FPGA_SDA
T
A
FPGA_SEN
FPGA_RST
J15
CONN_QTH_30X2-D-A
J15
CONN_QTH_30X2-D-A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
1
1
13
15
17
19
21
23
25
27
29
31
33
35
37
39
G1
G2
G3
G4
G5
G6
G7
G8
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
1
10
1
1
1
1
12
1
13
1
14
1
15
1
16
1
17
1
18
1
19
120
S005
Physical Description
Figure 14. Sheet 5 of 5
SLAU196 – April 2007
25
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