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Circuit Description
Table 5. EVM Analog Input Options
EVM
Jumper Changes
Voltage on J11
Evaluation Goal
Analog signal to ADC
Comments
Option
Required
and J13
SJP1
→
1-2
Evaluate ADC
SJP2
→
1-2
From J6 (Channel A) or
1
performance using direct
SJP3
→
No shunt
Do not connect
Default
J3 (Channel B)
input to ADC
SJP5
→
1-2
JP3
→
2-3
SJP1
→
2-3
SJP2
→
2-3
SJP3
→
2-3
Evaluate ADC
Signal from J3 and J9
Used if input
SJP5
→
2-3
J11
→
5V
2
performance using input
is amplified by
signal requires
JP3
→
1-2
J13
→
GND
through THS4509
THS4509
amplification
Install J9
Remove R63
Install R62
2.2.3.1
Analog Input Option 1
Option 1 supplies the transformer-coupled input from J6 or J3 to the ADC. This configuration is the default
on the EVM. The test result using this option is shown in
. A double-transformer input circuit is
used to provide better differential to single-ended conversion than a single transformer can provide. The
transformers used are both of a 1:1 turns ratio, so termination of the 50
Ω
input signal path after the
transformers can be two 25
Ω
resistors terminated to the Common Mode Voltage (VCM) provided by the
ADC.
Following the transformer coupling, surface mount pads are provided for several input circuits. By default,
the input circuit is configured as shown in the ADS62PXX data sheet under the recommended input circuit
for high-bandwidth (>100 MHz IF) inputs. However, the recommended low-bandwidth input circuit for the
ADS62PXX can be implemented on the surface mount pads provided.
2.2.3.2
Analog Input Option 2
Option 2 allows the use of an amplifier to provide input to the ADC. TI has a range of wideband
operational amplifiers such as THS4508/09/11/13/20. On this EVM, THS4509 is used as an example to
amplify the input from J3 or J9. The THS4509 is powered up by applying 5 V to J11 and GND to J13 (for
AC coupled configuration). A differential power supply (4V applied to J11 and -1V applied to J13) may also
be used to power up the amplifier if common-mode biasing is an issue for DC-coupled applications. See
the THS4509 data sheet (
). The output of the THS4509 is filtered through a band-pass filter
before ADC input. The band-pass filter can be designed depending on the end application. By default, the
band-pass filter components are not populated because the filter design depends on the end application.
A key point when designing a filter is to design it for proper load termination. Care must be taken when
supplying the input to the board; the source impedance must be 50
Ω
. Results can vary due to
mismatching of the various source and termination impedances.
2.2.4
ADC Clock Input
The clock can be supplied to the ADC in one of several ways. The default clocking option is to supply a
single ended clock directly to the SMA connecter J19 directly, and this clock is converted to differential
and AC coupled to the ADC by transformer coupling. The clock input must be from a clean, low-jitter
source and is commonly filtered by a narrow bandpass filter. The clock amplitude is commonly set to
about 1.5V peak to peak, and the amplitude offset is not an issue due to the AC coupling of the clock
input. The clock source is commonly synchronized with the input frequency signal generator to keep the
clock and IF coherent for meaningful FFT analysis.
11
SLAU237B – May 2008 – Revised July 2010
ADS62PXXEVM
Copyright © 2008–2010, Texas Instruments Incorporated
