Texas Instruments ADS62PXXEVM, User Manual

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Connecting to FPGA Platforms
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4.1.1 Quick-Test Results
The user can make the jumper setting as mentioned in Table 1 . In this configuration, the EVM uses an
external clock source from J19 and a direct input signal J6 (Channel A) or J3 (Channel B) to the ADC.
This setup uses Power Option 1 (
Table 3 ), Analog Input Option 1 ( Table 5 ), and Clock Option 1 ( Table 7 ),
which is the default on the EVM. Figure 9 shows the ADC performance capture using TSW1200 with the
input signal of a 57.6-MHz frequency and clock frequency of 250 MHz with ADS62PXX.
Figure 9. Quick-Setup Test Result
20 ADS62PXXEVM SLAU237B – May 2008 – Revised July 2010
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