Revision Changes
www.ti.com
5.2
Coherent Input Frequency Selection
Typical ADC analysis requires users to collect the resulting time-domain data and perform a Fourier
transform to analyze the data in the frequency domain. A stipulation of the Fourier transform is that the
signal must be continuous-time; however, this is impractical when looking at a finite set of ADC samples,
usually collected from a logic analyzer. Consequently, users typically apply a window function to minimize
the time-domain discontinuities that arise when analyzing a finite set of samples. For ADC analysis,
window functions have their own frequency signatures or lobes that distort both SNR and SFDR
measurements of the ADC.
TI uses the concept of coherent sampling to work around the use of a window function. The central
premise of coherent sampling entails that the input signal into the ADC is carefully chosen such that when
a continuous-time signal is reconstructed from a finite sample set, no time-domain discontinuities exist. To
achieve this, the input frequency must be an integer multiple of the ratio of the ADC sample rate (f
s
) and
the number of samples collected from the logic analyzer (N
s
). The ratio of f
s
to N
s
is typically referred to as
the fundamental frequency (f
f
). Determining the ADC input frequency is a two-step process. First, select
the frequency of interest for evaluating the ADC; then, divide this by the fundamental frequency. This
typically yields a non-integer value, which should be rounded to the nearest odd, preferably prime, integer.
Once that integer, or frequency bin (f
bin
), has been determined, multiply this with the fundamental
frequency to obtain a coherent frequency to program into their ADC input signal generator. The procedure
is summarized as follows.
f
f
= f
s
/N
s
f
bin
= Odd_round(f
desired
/f
f
)
Coherent frequency = f
f
× f
bin
6
Revision Changes
Changes from Revision C. to Revision D.
•
Modified the layout of input and output decoupling path for the DC/DC power supply and LDO.
•
Added power jack J17 to allow 5V power brick input.
•
Changed LDO U14 to allow higher 5V input current.
•
Modified the layout and jumper settings of the ADC input clock path from the external clock source or
clock distribution chip (U10) output.
•
Added external SPI connector J22 to allow external SPI control input to the clock distribution chip
(U10).
•
Changed USB-to-SPI Controller IC from U4 in Rev. C to U6 in Rev. D to minimize the physical size of
the SPI controller.
•
Changed USB connector from J5 in Rev. C to J16 in Rev. D to minimize the physical size of the USB
connector.
24
ADS62PXXEVM
SLAU237B – May 2008 – Revised July 2010
Copyright © 2008–2010, Texas Instruments Incorporated
