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2.3 JESD204B Translation Card
The block diagram for the JESD204B Translation card is shown in Figure 1 . The various inputs, outputs,
switches and jumpers are described in Table 4 . The configuration file required by the FPGA is stored in
the on-board EEPROM U8. Upon power up or pressing switch SW9, the contents of U8 are loaded into
the FPGA. This process takes about 5-10 seconds, once completed, the FPGA_DONE LED illuminates.
The current configuration only supports one mode of JESD204B operation. This mode is as follows:
• 4 lanes per link (L)
• 2 converters per device (M)
• 1 octet per frame clock period (F)
• 20 frames per multiframe (K)
• 1 sample per frame (S)
• Subclass 1
• ADC sample rate 250 MHz
• SerDes rate 2500 MHz
Future GUI software releases will support multiple configurations using a USB interface to configure the
FPGA.
The design of the JESD204B Translation card is similar to the Xilinx Kintex-7 FPGA KC705 Evaluation Kit.
The JESD204B receive function inside the Kintex 7 FPGA on the JESD204B Translation card implements
the Xilinx Core Generator JESD204 function. Details about this core, Xilinx devices, software tools, and
license required by this core, can be found at www.xilinx.com”
Table 4. Input and Output Connectors, Jumpers and Switches Description of the JESD204B
Translation Card
Component Description
J4 JESD204B FMC connector. Interfaces to ADS42JBx9EVM J3
J2 (TSW1400 ADC) LVDS connector. Interfaces to TSW1400 ADC_INTERFACE
connector J3
J3 (TSW1400 DAC) LVDS connector. Interfaces to TSW1400 DAC_INTERFACE
connector J4
J10 (Test connector) Test header
J11 (JTAG) JTAG interface to FPGA
J12 (EEPROM PROG) EEPROM programming interface connector
J15 (+5V IN) 5-V power supply input
J13 (USB) USB interface connector. Not used.
J17-J20 Spare transceiver I/O’s
J7 (SPARE1) CMOS 10-MHz output
J8, J6 Spare I/O connectors
J5 Spare input clock or I/O connector
J9 Spare Input clock connector
J16 Spare TSW1400 DAC clock source
J1 (FAN PWR) For use with FPGA fan. Currently not required.
J14 (PWR MON) Power monitor U12 programming interface connector
SW2 & SW4 Spare dipswitches connected to spare FPGA inputs
SW1, SW3 & SW5 Spare pushbutton connected to spare FPGA inputs
SW6 (CPU RESET) FPGA hardware reset
SW9 (FPGA_PROG_B) FPGA reconfiguration switch. Causes the FPGA to load
configuration from EEPROM.
SW8 (MSEL) Sets programming mode of FPGA. Default is 1, 2, 3, 5 off and 4
on
SW10 (UCD Reset) Power monitor U12 reset
14 ADS42JBx9 System Evaluation Kit SLAU468A – November 2012
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