background image

A0

1

A1

2

A2

3

VSS

4

SDA

5

SCL

6

WP

7

VCC

8

U5

BR24G32FVT-3AGE2

ISO_GND

EVM_ID_PWR

EVM_ID_PWR

EVM_ID_PWR

ISO_GND

0.1uF

C36

0.1uF

C41

ISO_GND

10k

R98

EVM_ID_SCL

EVM_ID_SDA

WP

ISO_GND

ISO_3V3

0.1µF

C38

ISO_GND

ISO_GND

ISO_3V3

0.1µF

C39

ISO_GND

0

R100

XFMR_CLK

1

2

3

4

5

J10

EXT_CLK

ISO_GND

ISO_GND

VDD

4

OE

1

GND

2

CLOCK OUT

3

Y1

ISO_3V3

1.00k

R104

ISO_3V3

JP5

OSC_EN

ISO_GND

0.1µF

C43

ISO_GND

ISO_ADC_CLK

VCC

2

CLK

6

D1

1

D2

3

EN

5

GND

4

SN6505BQDBVTQ1

U6

ISO_3V3

0

R96

ISO_VCC

ISO_VCC

ISO_VCC

ISO_GND

ISO_GND

ISO_GND

DGND

VADC_HV

0.1µF

C30

DGND

0

R99

DNP

ISO_GND

0.1µF

C37

D2

RB168MM-40TR

D1

RB168MM-40TR

XFMR_CLK

1.00k

R95

ISO_VCC

JP4

XFMR_EN

VCC1

1

INA

2

INB

3

INC

4

IND

5

INE

6

OUTF

7

GND1

8

GND2

9

OUTD

12

OUTC

13

OUTB

14

OUTA

15

VCC2

16

OUTE

11

INF

10

ISO7761FQDWQ1

U4

DRDY

GPIO2/FAULT

GPIO3/OCCA

GPIO4/OCCB

RESET

GPIO1

ADC DIGITAL

DGND

ISO_GPIO2/FAULT

ISO_GPIO1

ISO_DRDY

ISO_GPIO3/OCCA

ISO_GPIO4/OCCB

ISO_SDO

ISO_GPIO0/MHD

DGND

GPIO0/MHD

CLK

SCLK

CS

SDO

SDI

ADC DIGITAL

ADC_IOVDD

ISO_3V3

ISO_GND

ISO_GND

QTH-030-01-L-D-A

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

GND

MP1

GND

MP2

GND

MP3

GND

MP4

J9

ISO_GND

ISO_GND

EVM_RAW_5V

ISO_3V3

ISO_GND

Digital Interface

EVM_ID_PWR

0

R103

ISO_GND

EVM_ID_SCL

EVM_ID_SDA

0

R101

0

R102

ISO_GND

WP

EVM_REG_5V5

ISO_GND

ISO_SDI

ISO_CS
ISO_SCLK

ISO_DRDY

ISO_RESET

ISO_GPIO2/FAULT

ISO_GPIO1

ISO_GPIO0/MHD

EVM_RAW_5V

0

R97

DNP

0.1µF

C31

DGND

0.1µF

C33

ISO_GND

ADC_IOVDD

ISO_3V3

0.1µF

C32

DGND

0.1µF

C34

ISO_GND

VCC1

1

INA

2

INB

3

INC

4

IND

5

INE

11

INF

10

GND1

8

GND2

9

OUTD

12

OUTC

13

OUTB

14

OUTA

15

VCC2

16

OUTE

6

OUTF

7

ISO7762FQDWQ1

U3

TP8

ISO_VCC

2

6

3

1

4

5

T1

750313769

ISO_RESET

ISO_SDI

ISO_SCLK

ISO_CS

ISO_ADC_CLK

1CLK

1

1D

2

1Q

7

SN74AUP2G80DCUR

U8A

1CLK

1

1D

2

1Q

7

SN74AUP2G80DCUR

U7A

2CLK

5

2D

6

2Q

3

SN74AUP2G80DCUR

U7B

VCC

8

GND

4

SN74AUP2G80DCUR

U8C

VCC

8

GND

4

SN74AUP2G80DCUR

U7C

2CLK

5

2D

6

2Q

3

SN74AUP2G80DCUR

U8B

33.0

R88

33.0

R87

33.0

R86

33.0

R85

33.0

R84

33.0

R83

33.0

R89

33.0

R90

33.0

R91

33.0

R92

33.0

R93

33.0

R94

ISO_GPIO3/OCCA
ISO_GPIO4/OCCB

10uF

C42

10uF

C40

10uF

C35

10uF

C29

1µF

C44

1µF

C45

ISO_SDO

ADC_DIGITAL

ADC_DIGITAL

Is

o

la

ti

o

n

B

a

rr

ie

r

ISO_CAPCLK

VADC_HV:

1. VCC = 3.3 V (3V3_IOVDD),

VADC_HV = 5.61 V

2. VCC = 5 V (EVM_RAW_5V)

VADC_HV = 8.5 V

Internal SN6505B fsw = 420 kHz when
XFMR_CLK is floating.

ADC fmod is 4.096 MHz with CLK = 8.192 MHz.

Suggest clocking transformer driver at CLK / 16 =
512 kHz (SN6505B uses internal XFMR_CLK / 2
-> fsw = 256 kHz).

Populate 0-ohm to ISO_GND on CLK pin for
SN6501.

ISO776x "F" devices
default output LOW

Figure 7-8. Digital Isolators, DC/DC Power Supply, External Clock, and PHI Controller

ADS131B26Q1EVM-PDK Bill of Materials, PCB Layout, and Schematics

www.ti.com

30

ADS131B26Q1EVM-PDK Evaluation Module

SBAU413 – OCTOBER 2022

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Copyright © 2022 Texas Instruments Incorporated

Summary of Contents for ADS131B26Q1EVM-PDK

Page 1: ...y current and battery pack voltage with high resolution and accuracy The EVM allows evaluation of all aspects of the ADS131B26 Q1 This user s guide covers the operation of the ADS131B26Q1EVM PDK Throu...

Page 2: ...re 2 3 ADC3A Voltage Input Circuit Schematic 8 Figure 3 1 External ADC Clock Options Schematic 10 Figure 4 1 DC DC Converter and Transformer Driver Circuit Schematic 11 Figure 4 2 ADC Analog and Digit...

Page 3: ...gs 13 Table 5 2 Nominal Voltages Default Configuration 14 Table 7 1 ADS131B26Q1EVM PDK Bill of Materials 24 Trademarks LabVIEW is a registered trademark of National Instruments All trademarks are the...

Page 4: ...tions DC DC converter output provides APWR and DPWR supplies which the ADC uses to generate AVDD and DVDD with the respective integrated low dropout regulators LDOs APWR and DPWR can be provided exter...

Page 5: ...software and power is supplied to the EVM The default installation path is C Program Files x86 Texas Instruments ADS131B26 Q1 EVM 5 When the GUI finishes loading and is connected to the EVM hardware t...

Page 6: ...input or general purpose digital input output 10 V to 10 V Gain 4 VPB GPIO0B 3 Differential current negative input Shorted to AGND default CNB 4 Differential current positive input 0 mA to 12 5 mA Ga...

Page 7: ...and ADC2B The ADS131B26 Q1 features two multiplexed 16 bit ADC channels that are intended to measure shunt temperature using external temperature sensors and other voltages in the system For demonstr...

Page 8: ...5 At gain 4 which allows an input voltage from 10 V to 10 V on the positive voltage measurement inputs VPA and VPB The negative voltage measurement inputs VNA and VNB are connected to AGND by default...

Page 9: ...controller side of the EVM ISO_GPIO0 MHD J9 6 General purpose digital input output 0 or missing host detect output ISO_GPIO1 J9 8 General purpose digital input output 1 ISO_GPIO2 FAULT J9 10 General p...

Page 10: ...digital circuitry inside the device The ADC modulator frequency fMOD is equal to one half the clock frequency fMOD fCLK 2 and controls the timing of the input sample and hold switches inside each delt...

Page 11: ...ing frequency This clock operates asynchronously to the ADS131B26 Q1 internal clock CLK 8 192 MHz However the EVM also supports an external ADC clock which can be provided either by enabling the onboa...

Page 12: ...analog and digital ADC supply options Figure 4 2 ADC Analog and Digital Supply Options Schematic 4 3 Power Supply and Voltage Reference Decoupling The power supply and ADC voltage reference pins for...

Page 13: ...ult shunts Figure 5 1 ADS131B26Q1 PDK Jumper Default Settings Table 5 1 Default Jumper Settings Designator Position Function JP1 1 2 RCAPA is selected as bias voltage for the TMP61 JP2 2 3 Selects the...

Page 14: ...tware folder of the ADS131B26Q1EVM PDK and run the GUI installer to install the EVM GUI software on your computer CAUTION Manually disable any antivirus software running on the computer before downloa...

Page 15: ...Install this driver software anyway The ADS131B26Q1EVM PDK requires the LabVIEW run time engine and may prompt for the installation of this software as shown in Figure 5 4 if not already installed Fi...

Page 16: ...on changes In the Data Capture Configuration section are basic settings and controls to initiate a data capture from the main ADC channels OSR13A and OSR13B allow data rates to be configured for ADC1A...

Page 17: ...gister Map Configuration tool has three distinct views that summarize the current register map configuration At the top of the window is a tabular view where registers are listed in order of ascending...

Page 18: ...Settings for ADC1A and ADC3A and Global Settings for ADC1B and ADC3B which contain the register settings from addresses 82h and C2h respectively Below the global channel settings are individual ADC c...

Page 19: ...teps Steps 0 through 7 are displayed on the page by default and steps 8 through 15 can be displayed by selecting the corresponding tab on the bottom of each section Each step allows the following sett...

Page 20: ...ollects the specified number of samples for all channels but some conversion data are missed from the faster channels reducing the effective data rate Initiate a data capture by specifying the number...

Page 21: ...of non coherent sampling The 7 Term Blackman Harris window is the default option and has sufficient dynamic range to resolve the frequency components of a 24 bit ADC The None option corresponds to not...

Page 22: ...t s Rule by default This method minimizes the mean squared error in the bin approximation assuming the data follows a Gaussian distribution Alternatively select Custom under the Binning Rule drop down...

Page 23: ...of measurements after each DRDYn falling edge For demonstration purposes the GUI configures ADC1A and ADC1B to use the highest OSR setting which produces the minimum data rate and allows the maximum t...

Page 24: ...C19 C22 C23 C25 C28 C44 C45 8 1uF CAP CERM 1 uF 25 V 10 X7R 0603 603 C0603C105K 3RACTU Kemet C24 1 0 22uF CAP CERM 0 22 uF 25 V 5 X7R 0603 603 C0603C224J 3RAC7867 Kemet C29 C35 C40 C42 4 10uF CAP CERM...

Page 25: ...103 07 G S Samtec JP4 JP5 2 Header 100mil 2x1 Gold TH 2x1 Header TSW 102 07 G S Samtec LBL1 1 Thermal Transfer Printable Labels 0 650 W x 0 200 H 10 000 per roll PCB Label 0 650 x 0 200 inch THT 14 4...

Page 26: ...R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 11 100k RES 100 k 1 0 1 W 0603 603 RC0603FR 0 7100KL Yageo R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 12 33 RES 33 0 1 0 1 W 0603 603 RC0603FR 0 733RL...

Page 27: ...Speed Robust EMC Six Channel Digital Isolators DW0016B SOIC 16 DW0016B ISO7762FQD WQ1 Texas Instruments ISO7762FQD WRQ1 Texas Instruments U4 1 High Speed Robust EMC Reinforced Six Channel Digital Iso...

Page 28: ...2 Top Layer Figure 7 3 Ground Layer Figure 7 4 Power Layer Figure 7 5 Bottom Layer Figure 7 6 Bottom Silkscreen ADS131B26Q1EVM PDK Bill of Materials PCB Layout and Schematics www ti com 28 ADS131B26Q...

Page 29: ...52 1 96k R56 13 7k R58 13 7k R59 1 96k R63 AGND ADC2B_V3B V3B AGND ADC2B_V4B V4B ADC2B_V6B V6B AGND ADC2B_V1B V1B AGND ADC2B_V2B V2B 10 5k R17 ADC2B_V5B V5B 10 5k R36 100nF C4 100nF C11 100nF C13 100n...

Page 30: ...3V3 ISO_GND Digital Interface EVM_ID_PWR 0 R103 ISO_GND EVM_ID_SCL EVM_ID_SDA 0 R101 0 R102 ISO_GND WP EVM_REG_5V5 ISO_GND ISO_SDI ISO_CS ISO_SCLK ISO_DRDY ISO_RESET ISO_GPIO2 FAULT ISO_GPIO1 ISO_GPIO...

Page 31: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 32: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 33: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 34: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 35: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 36: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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