4.2 ADC Power Supplies
The transformer output is connected to two rectification diodes (D1 and D2) to provide the main high-side supply
voltage (
VADC_HV
). JP2 and JP3 connect
VADC_HV
to the ADC APWR and DPWR supply pins, respectively.
The ADS131B26-Q1 uses two internal LDOs to generate the primary analog and digital supplies (
AVDD
and
IOVDD
). When JP2 and JP3 are installed in the [2-3] position,
VADC_HV
is nominally approximately 5.1 V. To
evaluate the ADS131B26-Q1 with an external APWR and DPWR supply, uninstall the jumpers on JP2 and JP3
and connect the external supply to the corresponding terminal block inputs (J6 and J8). Alternatively, the ADC
internal LDOs can be completely bypassed by moving both JP2 and JP3 jumpers to the [1-2] position. In this
configuration, APWR must be between 3 V and 3.6 V, and DPWR must be between 3 V and 5.5 V.
shows the analog and digital ADC supply options.
Figure 4-2. ADC Analog and Digital Supply Options (Schematic)
4.3 Power Supply and Voltage Reference Decoupling
The power supply and ADC voltage reference pins for the ADS131B26-Q1 are bypassed with ceramic capacitors
placed close to the supply pins. Additionally, the EVM layout uses thick traces or large copper fill areas, where
possible, between bypass capacitors and loads to minimize inductance along the load current path.
The EVM schematic lists the analog and digital grounds (
AGND
and
DGND
) as separate net names for the
purpose of circuit illustration. However, these two nets are connected on the EVM by a net-tie on the bottom
signal layer. Proper component placement and solid ground pours are important to make sure that the lowest
noise and highest accuracy is used in any precision ADC application. See
practices.
Power Supplies
12
ADS131B26Q1EVM-PDK Evaluation Module
SBAU413 – OCTOBER 2022
Copyright © 2022 Texas Instruments Incorporated
