3 Digital Filter
ADS126xEVM Software
3.4.3
Tab 3: Digital Filter
Tab 3 contains the filter and data rate selection controls, as shown in
Figure 19. Tab 3 Settings
The
ADC1 Filter Settings
section controls both the digital filter type and the data rate for ADC1. When the
FIR
filter is selected, data rates are limited to frequencies that support 50-Hz or 60-Hz line cycle rejection.
Note that because of speed limitations within the firmware, the 19.2 kSPS and 38.4 kSPS data rates are
only available when
Data Collection Mode
is set to
ADC1
on Tab 7 (
Data \ MODE
).
The
ADC2 Filter Settings
controls are shown only when an ADS1263EVM is connected. The SINC3 filter
is the only filter available for ADC2.
NOTE:
Data from ADC2 are only collected when
Data Collection Mode
is set to
ADC1 + ADC2
on
Tab 7 (
Data \ MODE
).
ADC2 Data Rate
must be at least ½ the
ADC1 Data Rate
setting because the firmware only
polls for new ADC2 data when an ADC1 conversion completes. Setting the
ADC2 Data Rate
much slower than ½ the
ADC1 Data Rate
may require a much longer collection time.
ADC1 and ADC2 do not sample simultaneously.
Changing ADC filter and data rate settings, the chopping settings on tab 4 (
IDAC \ Sensor Bias
), or the
fCLK
control, updates the
Filter Response
plot. This plot can be scaled by the controls below the plot or by
clicking and typing a new value into an existing axis value.
NOTE:
Make sure that the
fCLK
frequency input is correct (there is no need to modify fCLK when
using the ADS126x internal oscillator or the ADS126xEVM's default X1 crystal).
The
fCLK
frequency affects the calculated
ADC1 Data Rate
and
ADC2 Data Rate
indicators
that are also used by the software when acquiring data, plotting the filter response, or
calculating the FFT in the
MultiFFT
test plugin.
22
ADS126xEVM-PDK
SBAU206 – April 2015
Copyright © 2015, Texas Instruments Incorporated