TCP872 V1.0 User Manual Issue 1.1
Page 10 of 16
3.2 Address Mapping TCP872 – CardBus mode
The PCI1520 provides a window mechanism to link the PCI space to 32 bit CardBus cards address
spaces. Memory and I/O windows are programmable by the host software in the memory or I/O Base
Registers in the PCI1520 configuration space. The PCI1520 offers two memory and two I/O windows
per socket. The size of each window will be determined by host software via memory and I/O limit
registers. The Base Address Registers will be initialized with the start addresses and the limit registers
will be initialized with the upper address of the memory or I/O windows.
The CardBus card address space can be accessed via the CardBus base address registers, which are
located in the PCI configuration space of the PCI1520.
Figure 3-3 : CardBus window mechanism
The PCI1520 provides CardBus card status information via the CardBus Socket Register at
configuration space offset 0x10. This address, which must be initialized by the device driver software,
points to five 32 bit registers, which can be located anywhere in the PCI memory space at a 1 Kbytes
boundary at offset 0x00. Each socket has a separate base address register to access the CardBus
socket registers. The following socket registers are implemented in the PCI1520:
Register Name
Offset
Socket Event
0x00
Socket Mask
0x04
Socket Present State
0x08
Socket Force Event
0x0C
Socket Control
0x10
Reserved 0x14
Reserved 0x18
Reserved 0x1C
Socket Power Management
0x20
Figure 3-4 : Socket Registers implemented in PCI1520 (Function 0 and 1)
These registers may notify the device driver software that a card has been inserted, removed, and
what supply voltage is needed to power the CardBus card properly etc.
Further information regarding the status of the CardBus interface can be obtained from the secondary
status register at offset 0x16 in the PCI configuration space of the PCI1520. This register is very
similar to the PCI Bus Status Register and provides information about parity errors, aborted
transactions, CardBus system errors etc.
For detailed register description, please refer to PCI1520 data sheet which is part of the TCP872-ED
Engineering Documentation.
