TAMC900 User Manual Issue 2.0.1
Page 49 of 71
The first local Clock (LCLK_250) is an on board 250 MHz oscillator with LVDS signaling. It is possible to turn
the oscillator off via the on board CPLD. The second local clock is a 50 MHz (single ended) clock. The
following table provides the pin assignment of the FPGA local clock inputs:
Signal Name
Virtex-5 Pin
L D15
LCLK_250- E15
LCLK_50 AC14
Table 11-1: FPGA Local Clock (LCLK_250) Inputs
The two FPGA Clock outputs (CLKOUT0 and CLKOUT1) provide the ability to run the ADCs with user
specified clocks that are generated in the FPGA. The following table provides the pin assignment of the clock
outputs:
Signal Name
Virtex-5 Pin
to ADC
V5_ V6
V5_CLKOUT 0-
V7
0 – 3
V5_CLKOUT 1+
J5
V5_CLKOUT 1-
J6
4 – 7
Table 11-2: FPGA Clock Outputs
The TAMC900 provide two feedback clocks (MUX0_FB and MUX1_FB) that return the ADC clocks back to
the FPGA. The following table provides the pin assignment of the feedback clock inputs:
Signal Name
Virtex-5 Pin
from ADC
E13
MUX0_FB- E12
0 – 3
E18
MUX1_FB- F19
4 – 7
Table 11-3: ADC Feedback Clocks