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Tews Technologies TAMC900 User Manual Download Page 23

 

 

TAMC900 User Manual Issue 2.0.1 

Page 23 of 71 

4.7.4  Channel Start/Stop 

There are some constraints on the configurability of a channel in context of its channel group initially 
mentioned in this chapter. Additionally, the channel start conditions for data processing are summarized 
afterwards. 

The DMA operation can be performed if 

•

  DMA operation is enabled 

•

  a valid DMA descriptor is defined and loaded 

•

  the associated QDR-II memory is ready for use 

•

  the Channel Group Trigger is configured 

•

  the channel itself (channel configuration) is enabled 

•

  the channel’s global control bits are set 

 

If one condition is not met, the corresponding channel cannot be used. 

 

Besides these conditions it has to be considered that the QDR-II memories have been filled with valid data 
as far as required for Pre-Trigger Data Gathering if used. 

An active channel is stopped automatically if its associated Linked List has been processed. Stopping the 
processing while it is running (if necessary) should be done via the DMA Enable Bit (see chapter “Channel 
Activation”). 

 

Since the channels are handled concurrently the length of the channel DMA windows is 
defined separately. Consequently, one channel can still be active while the others the group 
have already finished. 

 

4.8 Restrictions 

4.8.1  Processing Limit 

The PCI Express adaptation is currently limited to 1 GByte/sec. Due to header overhead a fraction of 
approximately 88.89% (888 MByte/sec) can be 

continuously

 transmitted via the module. Exceeding this 

limitation causes the DMA processing to stop after the internal buffer structure has collapsed. 

For all channels at least 256 k samples can be obtained independently of the transmission rate caused by 
the integration of the QDR-II memory in the transmission path (refer chapter “Tracking Buffer”). 

 

The amount of data can be composed over all channels. 

 

Summary of Contents for TAMC900

Page 1: ...00 AMC with 8 high Speed ADCs 105MSps 14Bit Version 2 0 User Manual Issue 2 0 1 April 2010 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19 e m...

Page 2: ...e right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described he...

Page 3: ...chapter 4 3 May 2008 1 2 Corrections in Crosspoint Switch Control Register Different minor corrections and additions August 2008 1 0 3 New User Manual Issue Notation Correction of MMC JTAG Connector P...

Page 4: ...1 Channel Reset 21 4 7 2 Channel Activation 21 4 7 3 Descriptor Change 22 4 7 4 Channel Start Stop 23 4 8 Restrictions 23 4 8 1 Processing Limit 23 5 ADDRESS MAP 24 5 1 PCI Express Configuration 24 5...

Page 5: ...0x07 53 13 2 2 SiCA Input Register 1 Address 0x08 53 13 2 3 SiCA Input Register 2 Address 0x09 54 13 2 4 SiCA Output Register 1 Address 0x0A 54 13 2 5 SiCA Output Register 2 Address 0x0B 54 13 2 6 Si...

Page 6: ...ge 6 of 71 16 ON BOARD INDICATORS 65 16 1 DONE LED 65 16 2 Power Good LEDs 65 17 PIN ASSIGNMENT 66 17 1 Overview 66 17 2 I O Connector 67 17 3 MMC JTAG Connector Factory Use Only 69 17 4 Payload JTAG...

Page 7: ...8 CHANNEL DMA BASE DESCRIPTOR ADDRESS REGISTER 35 TABLE 6 9 CHANNEL PRE TRIGGER DATA REGISTER ADDRESS 0X64 0X4 CHANNEL 35 TABLE 6 10 CHANNEL DATA REGISTER ADDRESS 0X84 0X4 CHANNEL 36 TABLE 6 11 GLOBA...

Page 8: ...LOCK MUX CONTROL REGISTER ADDRESS 0X11 57 TABLE 13 11 JITTER ATTENUATOR CONTROL REGISTER ADDRESS 0X12 58 TABLE 13 12 GENERAL BOARD CONTROL REGISTER ADDRESS 0X18 59 TABLE 14 1 I O MATING CONNECTORS 61...

Page 9: ...NSIONS 46 FIGURE 10 1 QDR II SRAM INTERFACE 47 FIGURE 11 1 CLOCK DISTRIBUTION BLOCK DIAGRAM 48 FIGURE 13 1 TIMING OF FPGA CPLD INTERFACE 51 FIGURE 14 1 TAMC900 CONNECTOR AND STANDOFF POSITIONS 60 FIGU...

Page 10: ...f the ADCs in two groups The trigger inputs are routed to the FPGA Eight LTC2254 ADCs provide up to 105 MSps and 14 bit resolution each The minimum sample rate is 1 Msps 4 MByte high speed on board SR...

Page 11: ...oltage differential 2VP P ADC input common mode Voltage 1V to 1 9V ADC INL DNL Error 1 0 5 LSB typical Number of Clock Inputs 3 differential LVDS Number of Trigger Inputs 3 differential LVDS I O Conne...

Page 12: ...ll be damaged if higher voltage levels are applied 3 1 ESD Protection The TAMC900 is sensitive to static electricity Packing unpacking and all other handling of the TAMC900 has to be done in an ESD EO...

Page 13: ...losed Pushed all way in OFF Module is ready powered Table 3 1 AMC Module Insertion When the blue LED does not go off but returns to the ON state the module FRU information is invalid or the carrier ca...

Page 14: ...egisters Channel FIFO DMA Engine x8 Tracking Buffer x2 Channel Logic x2 DCMs AMC PCI Express Connection ADC Inputs Control Logic Clock Distribution Sample Rate Logic Trigger Inputs Sampling Clocks DMA...

Page 15: ...ted to simplify the data processing out of the target memory by mapping the ADC values into legal data types The sign extension method is described below In 2 th complement the ADC sign bit 13 is mapp...

Page 16: ...press transmission gaps the memory can buffer the data so that the data integrity is still held Based on the internal organization structure there are 256k words for a single channel At a sample frequ...

Page 17: ...sted sample count see below The Around Trigger Data Gathering is a mixture of the previous two modes It is used to obtain the data before and after the trigger event Thus it makes also use of the QDR...

Page 18: ...I Express traffic interrupts will only be generated if additional steering flags demand this After the last descriptor has been processed its successor list element is loaded Thus the last element mus...

Page 19: ...eparately allows process steering during runtime and offers a different handling of the descriptors Notice that changing the descriptors after channel activation is not recommended The flags are descr...

Page 20: ...that switching can be performed at every time Switching during runtime processing is not recommend In accordance with that both groups can be set into a common clock mode sourced from DCM0 or DCM1 or...

Page 21: ...nt if one has occurred is reset channel DMA information e g remaining window size are obsolete the DMA base descriptor as defined through the register map is loaded the current processed DMA transmiss...

Page 22: ...ead through the register interface the channel s DMA Base Descriptor Addresses register content is used to load DMA descriptor information DMA information e g Channel DMA Buffer Fill Level is set in t...

Page 23: ...if used An active channel is stopped automatically if its associated Linked List has been processed Stopping the processing while it is running if necessary should be done via the DMA Enable Bit see c...

Page 24: ...al Space PCI Base Address Offset in PCI Configuration Space PCI Space Mapping Size Byte Port Width Bit Endian Mode Description 0 0 0x10 MEM 1024 32 Little Register Space 1 1 0x14 MEM 8192 32 Little DM...

Page 25: ...Write 64 Bit Addressing Prohibit Error Message I O Read Prohibit Error Message I O Write Prohibit Error Message Read Locked 32 Bit Addressing Prohibit Error Message Read Locked 64 Bit Addressing Proh...

Page 26: ...gger Configuration 0 R W 8 0x0020 Trigger Configuration 1 R W 8 0x0024 Channel Configuration 0 R W 8 0x0028 Channel Configuration 1 R W 8 0x002C Channel Configuration 2 R W 8 0x0030 Channel Configurat...

Page 27: ...l DMA Status 1 R W 16 0x00B0 Channel DMA Status 2 R W 16 0x00B4 Channel DMA Status 3 R W 16 0x00B8 Channel DMA Status 4 R W 16 0x00BC Channel DMA Status 5 R W 16 0x00C0 Channel DMA Status 6 R W 16 0x0...

Page 28: ...QDR II Memory Controllers 1 PLL is locked 0 PLL is not locked R 0 15 13 Reserved R 0 12 STAT2 This bit indicates if the DCM 1 has been locked and operates correctly 1 DCM 1 locked 0 DCM 1 not locked R...

Page 29: ...ultiplication and division are grouped into a single data word This is due to the physical interface of a Virtex 5 DCM Bit Symbol Description Access Reset Value 15 8 MULT The selected multiplier is th...

Page 30: ...s reset after an event has processed 0 channel not armed 1 channel armed R W 0 7 CHEN7 6 CHEN6 5 CHEN5 4 CHEN4 3 CHEN3 2 CHEN2 1 CHEN1 0 CHEN0 A channel is enabled CHENx for internal processing if the...

Page 31: ...s channel specific Bit Symbol Description Access2 Reset Value 15 CRST7 R W 0 14 CRST6 R W 0 13 CRST5 R W 0 12 CRST4 R W 0 11 CRST3 R W 0 10 CRST2 R W 0 9 CRST1 R W 0 8 CRST0 Resetting a channel x is p...

Page 32: ...k source must be done considering the ADCs specification to avoid a physical damage Bit Symbol Description Access Reset Value 7 4 SRSC Sample Rate Source Configuration Selection Sample Clock 000x AMC...

Page 33: ...set Value 7 Reserved R 0 6 4 TMSEL Selection of the Trigger operation mode TMSEL Input Selection 000 Disabled 001 Around Trigger Data Gathering Others Reserved R W 0 3 0 TISEL Trigger input source and...

Page 34: ...ty Cycle Stabilizer 0 disabled 1 enabled R W 0 3 OFSEN Overflow Signalize Enable steers whether an ADC overflow signal is taken into the Channel DMA status register or not 0 suppress ADC overflow 1 co...

Page 35: ...This address points into the memory where the channel base address descriptor is placed R W 0 Table 6 8 Channel DMA Base Descriptor Address Register Address 0x44 0x4 Channel 6 9 Channel Pre Trigger Da...

Page 36: ...atic evaluation of the input data e g channel calibration The channel data is subdued a sign extension for both ADC operating modes 2 s complement and offset binary output format Bit Symbol Descriptio...

Page 37: ...ng channel interrupt source Bit Symbol Description Access Reset Value 7 ECH7 R 0 6 ECH6 R 0 5 ECH5 R 0 4 ECH4 R 0 3 ECH3 R 0 2 ECH2 R 0 1 ECH1 R 0 0 ECH0 The bits indicate an event ECHx on channel x 1...

Page 38: ...een processed that is the last of a Linked List R W 0 8 SEQHI Sequence Host Interrupt SEQHI is asserted if a Descriptor of a Linked List has been processed with the Host Interrupt flag set R W 0 7 2 R...

Page 39: ...Fill Level Register Address 0xC8 0x4 Channel The value after channel setup and activation is the one that has been read from the defined DMA base descriptor 6 14 Revision Control Register The registe...

Page 40: ...y The General DMA Status register can be used to detect which channel caused the interrupt The corresponding Channel DMA Status register must be read afterwards to obtain further information about the...

Page 41: ...JTAG Cain TEWS recommends setting the CPLD in Bypass Mode during FPGA or Platform Flash JTAG operations 8 2 MMC Interface The FPGA has the following signals which are connected to the MMC Interface D...

Page 42: ...AMC900 10 TX0 B2 44 TX0 C2 45 RX0 C1 47 RX0 D1 48 TX1 G2 50 TX1 F2 51 RX1 F1 53 RX1 E1 54 TX2 H2 59 TX2 J2 60 RX2 J1 62 RX2 K1 63 TX3 N2 65 TX3 M2 66 RX3 M1 68 RX3 L1 69 TX4 P2 91 TX4 R2 90 RX4 R1 88...

Page 43: ...possible 8 4 RAM Interface The RAM interface to access the QDR II SRAM of the TAMC900 has to be implemented in the FPGA TEWS recommends using the Xilinx Memory Interface Generator MIG to build the RA...

Page 44: ...default the TAMC900 sets the input voltage range of all ADCs to 2V The Common Mode Voltage of the ADC Differential Inputs is 1 5V 9 1 3 Input Frequency Range The LTC2254 provides a full power bandwidt...

Page 45: ...he input clock has a non 50 duty cycle Using the clock duty cycle stabilizer is recommended for most applications This circuit uses the rising edge of the CLK pin to sample the analog input The fallin...

Page 46: ...3 mm and sufficient cooling of the ADCs 18 50 mm 28 50 mm 10 90 mm 26 80 mm 29 90 mm 26 00 mm 20 60 mm 52 50 mm 22 80 mm 32 80 mm 34 30 mm 37 50 mm 31 70 mm 36 90 mm 55 30 mm 4 00 mm 8 40 mm 11 80 mm...

Page 47: ...D 17 0 A 17 0 RPS WPS BWS K K C C Q Q QDR II x18 SRAM DQ 17 0 D 17 0 A 17 0 RPS WPS BWS K K C C Q Q FPGA QDR II x18 SRAM Figure 10 1 QDR II SRAM Interface The TAMC900 uses 4 Burst SRAM to lower addre...

Page 48: ...4 ADC 5 ADC 6 ADC 7 Local Clocks Golbal Clock Buffer SY89540U ICS85314 11 ICS85314 11 ICS874003 02 Differential to LVTTL conversion of the ADC clock signals is done by MC100ES60T23 devices MGT_CLK GC...

Page 49: ...e two FPGA Clock outputs CLKOUT0 and CLKOUT1 provide the ability to run the ADCs with user specified clocks that are generated in the FPGA The following table provides the pin assignment of the clock...

Page 50: ...gramming provided by TEWS does not use these lines Care must be taken to avoid damaging the FPGA Signal Name Virtex 5 Pin SiCA Pin LVDS_0 K6 18 LVDS_0 K7 20 LVDS_1 K8 24 LVDS_1 L7 26 LVDS_2 M7 30 LVDS...

Page 51: ...the local FPGA clock Controlling of the jitter attenuator Control of the local clock distribution Please refer to the following subsections for more information 13 1 Interface to FPGA All functions of...

Page 52: ...DC 5 Control Register R W 0x02 0x06 ADC 6 Control Register R W 0x02 0x07 ADC 7 Control Register R W 0x02 0x08 SiCA Input Register 1 R depends on SiCA 0x09 SiCA Input Register 2 R depends on SiCA 0x0A...

Page 53: ...future use R 0 1 SHDN ADC Shutdown 0 normal operation 1 shutdown corresponding ADC R W 1 0 OE ADC output Enable enables the digital outputs of the ADC 0 output disable 1 output enable R W 0 Table 13...

Page 54: ...O_SiCA11 R W 0 2 O_SiCA10 R W 0 1 O_SiCA9 R W 0 0 O_SiCA8 The value written to this register is displayed to the SiCA on the corresponding SiCA general purpose pins if the pin is defined as output in...

Page 55: ...eneral purpose pins as input or output 0 CPLD input 1 CPLD output R W 0 Table 13 7 SiCA Output Enable Register 1 Address 0x0C 13 2 7 SiCA Output Enable Register 2 Address 0x0D Bit Symbol Description A...

Page 56: ...C 0 to 3 00 Clock input 0 SW_CLK0 100MHz PCIe Ref Clock 01 Clock input 1 EXT_CLK2 10 Clock input 2 EXT_CLK1 11 Clock input 3 EXT_CLK0 R W 0 3 OUT1_ SEL1 R W 0 2 OUT1_ SEL0 Clock Select for FPGA_CLK_IN...

Page 57: ...7 0 route clock from crosspoint switch to ADCs 1 route Clock from FPGA to ADCs R W 0 4 EN_47 Enable Clock outputs to ADC 4 to 7 0 disable 1 enable R W 0 3 R 0 2 reserved for future use R 0 1 SEL_03 S...

Page 58: ...IN 0 1 0 1 25x fIN 2 5x fIN 1 1 0 2 5x fIN 1 25x fIN 0 0 1 2 5x fIN 1x fIN 1 0 1 1x fIN 1 25x fIN 0 1 1 1 25x fIN 1x fIN 1 1 1 1 25x fIN 1 25x fIN Input frequency fIN should be 100 MHz AMC FCLKA R W 1...

Page 59: ...e use R 0 6 reserved for future use R 0 5 RAMDLL1 Disable DLL of RAM 1 0 enable 1 disable R W 0 4 RAMDLL0 Disable DLL of RAM 0 0 enable 1 disable R W 0 3 reserved for future use R 0 2 reserved for fut...

Page 60: ...eeded must be generated on the SiCA A 120 pin high speed connector from Samtec QSE 060 01 L D A is used on the TAMC900 to interface with the SiCA The pin assignment of this connector can be found in t...

Page 61: ...onent Height The height of the SiCA above the AMC depends on the mated stacking height of the connector used When selecting a stacking height care must be taken to ensure enough space for the I O conn...

Page 62: ...e TAMC900 offers 3 LEDs in the front panel and seven on board LEDs For a detailed description of the on board LEDs please refer to chapter On Board Indicators 15 1 1 Front Panel LEDs LED Color State D...

Page 63: ...Sensor of the Virtex 5 TEMP_ADC1 TEMP_ADC2 TEMP_RAM TEMP_V5 CORE Figure 15 1 Temperature Sensor Locations The TAMC900 provides access to two voltage sensors via IPMI VOLT_PAYLOAD monitors the 12V Pay...

Page 64: ...be used to transmit connectivity data from the MMC to the FPGA This may be necessary in applications that implement different kinds of connections from the FPGA to the AMC interface The implementation...

Page 65: ...ate Power Good of the local power supplies and successful FPGA configuration Figure 16 1 On Board Indicators 16 1 DONE LED The green DONE LED is located on the bottom side of the PCB It indicates that...

Page 66: ...gure 17 1 Connector Overview The TAMC900 interfaces to a Signal Conditioning Adapter that carries the I O connectors accessible through the front panel The TAMC900 has a 120 pin connector Samtec QSE 0...

Page 67: ..._IO_4 2 5 Volt CMOS 10 SiCA_PWR 6 Volt 11 GP_IO_5 2 5 Volt CMOS 12 SiCA_PWR 6 Volt 13 GP_IO_6 2 5 Volt CMOS 14 GND logic Ground 15 GP_IO_7 2 5 Volt CMOS 16 GND logic Ground 17 GP_IO_8 2 5 Volt CMOS 18...

Page 68: ...84 TRIG_0 LVDS 85 AIN_6 0 2 9 Volt 86 TRIG_0 LVDS 87 GND logic Ground 88 GND logic Ground 89 GND logic Ground 90 TRIG_1 LVDS 91 AIN_7 92 TRIG_1 LVDS 93 AIN_7 0 2 9 Volt 94 GND logic Ground 95 GND log...

Page 69: ...TDO 3 3V CMOS TTL 9 GND Logic Ground 10 TDI 3 3V CMOS TTL 11 GND Logic Ground 12 Do Not Connect 13 GND Logic Ground 14 Do Not Connect Table 17 3 Pin Assignment Payload JTAG Connector 17 5 AMC Connect...

Page 70: ...ogic Ground 57 PWR 12V Payload Power 114 Tx12 56 SCL_L IPMB L Clock 115 Tx12 Differential Signaling 55 GND Logic Ground 116 GND Logic Ground 54 Rx5 117 Rx13 53 Rx5 Differential Signaling 118 Rx13 Diff...

Page 71: ...ential Signaling 151 Tx18 Differential Signaling 19 GND Logic Ground 152 GND Logic Ground 18 PWR 12V Payload Power 153 Rx19 17 GA1 Geogr Address Input 154 Rx19 Differential Signaling 16 GND Logic Grou...

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