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73M1903 MODEM ANALOG FRONT END DEMO BOARD User’s Manual

Revision 1.2

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© Copyright 2005 TERIDIAN Semiconductor Corporation

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Summary of Contents for 73M1903

Page 1: ...32 Copyright 2005 TERIDIAN Semiconductor Corporation TERIDIAN 73M1903 Modem Analog Front End Demo Board USER S MANUAL July 15 2005 Version 1 2 TERIDIAN Semiconductor Corporation 6440 Oak Canyon Rd Irvine CA 92618 5201 Ph 714 508 8800 Fax 714 508 8878 http www teridiansemi com ...

Page 2: ...ducts other than expressly contained in the Company s warranty detailed in the TERIDIAN Semiconductor Corporation standard Terms and Conditions The company assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained he...

Page 3: ...03 MODEM ANALOG FRONT END DEMO BOARD User s Manual Revision 1 2 3 of 32 Copyright 2005 TERIDIAN Semiconductor Corporation 73M1903 MODEM ANALOG FRONT END IC DEMO BOARD USER S MANUAL July 15 2005 Revision 1 2 ...

Page 4: ...D LOOK 7 2 SYSTEM DESCRIPTION 11 2 1 MAFE INTERFACE 11 2 2 73M1903 Register map 13 2 3 73M1903 system initialization 14 3 HARDWARE DESCRIPTION 17 3 1 Board SETTING Jumpers and connectors 17 3 2 Board Hardware Specifications 20 4 APPENDIX 21 4 1 example of typical sample rate SETTINGs 21 4 2 Demo Board Schematic Diagram 22 4 3 Demo Board BILLs of materials 25 4 4 Demo Board PCB LAYOUT 28 4 5 73M190...

Page 5: ...atic Diagram of US high speed DAA 23 Figure 4 3 Schematic diagram of CTR21 DAA 24 Figure 4 4 TERIDIAN 73M1903 DEMO BOARD Silk Screen Top 28 Figure 4 5 TERIDIAN 73M1903 DEMO BOARD Top Signal Layer 28 Figure 4 6 TERIDIAN 73M1903 DEMO BOARD Bottom Signal Layer 29 Figure 4 7 TERIDIAN 73M1903 DEMO BOARD Supply Plane 29 Figure 4 8 TERIDIAN 73M1903 DEMO BOARD Ground Plane 30 List of Tables Table 2 1 73M1...

Page 6: ...73M1903 MODEM ANALOG FRONT END DEMO BOARD User s Manual Revision 1 2 6 of 32 Copyright 2005 TERIDIAN Semiconductor Corporation This page was intentionally left blank ...

Page 7: ...ble DAA telephone network interface The Demo Board allows the evaluation of the 73M1903 Modem Analog Front End chip for universal modem and Fax applications interfacing to DSPs or other high performance processors It is not intended for use with general purpose controllers 1 2 SAFETY AND ESD NOTES THE 73M1903 DEMO BOARD IS ESD SENSITIVE ESD PRECAUTIONS SHOULD BE TAKEN WHEN HANDLING THE DEMO BOARD ...

Page 8: ...DEM ANALOG FRONT END DEMO BOARD User s Manual Revision 1 2 8 of 32 Copyright 2005 TERIDIAN Semiconductor Corporation Figure 1 1 73M1903 Demo Board Figure 1 2 TERIDIAN 73M1903 Demo Board connected to a Host System ...

Page 9: ...n 1 2 9 of 32 Copyright 2005 TERIDIAN Semiconductor Corporation 73M1903 SCLK FSB SDIN TXAP TXAN RXAP RXAN DAA GPIO5 OH GPIO4 RING SDOUT PHONE Line POWER SUPPLY RESET XTAL 73M1903 Evaluation board OH RING Figure 1 3 Block diagram for the TERIDIAN 73M1903 Demo Board ...

Page 10: ...73M1903 MODEM ANALOG FRONT END DEMO BOARD User s Manual Revision 1 2 10 of 32 Copyright 2005 TERIDIAN Semiconductor Corporation This page was intentionally left blank ...

Page 11: ...a DSP This serial data port is a bi directional port that can be supported by most DSPs with a synchronous serial port or GPIO that can be configured as a serial port The MAFE operates as a master device meaning it controls the timing and data flow The processor or DSP sends and receives data and control information based on the FS and SCLK signals provided by the 73M1903 SCLK FSB OSCIN SDIN SDOUT...

Page 12: ...5 RX4 RX3 RX2 RX1 RX0 SCLK SDOUT SDIN FSB TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 SCLK SDOUT SDIN FSB Data Frame with Early Frame Sync Data Frame with Late Frame Sync R W A6 A5 A4 A3 A2 A1 A0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 0 0 0 0 0 0 0 0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Control Frame Data format SC...

Page 13: ...detail in 73M1903 datasheet For more information please refer to the datasheet ADRESS Default BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00 08h ENFE TXBST1 TXBST0 TXDIS RXG1 RXG0 RXGAIN 01 00h TMEN DIGLB ANALB INTLB RXPULL SPOS HC 02 FFh GPIO7 GPIO 6 GPIO 5 GPIO 4 GPIO 3 GPIO 2 GPIO 1 GPIO 0 03 FFh DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 04 00h ENGPIO7 ENGPIO6 ENGPIO5 ENGPIO4 ENGPIO3 ENGPIO2 ...

Page 14: ...TROLLED CONTROL FRAME 1 Set TXD Bit 0 to 1 to request a control frame 2 Write or read the 73M1903 register using the MAFE control data format 3 Make sure to clear TXD bit 0 to 0 if another control frame is not needed HARDWARE CONTROLLED CONTROL FRAME 1 Set TXD Bit 0 to 1 to request a subsequent control frame 2 SET HC bit Reg01 bit0 using the MAFE control data format in the next frame There will no...

Page 15: ...ntrolled control frame CTRL_FRAME CTRL13 0x00 Force to Xtal clock CTRL_FRAME CTRL1 ENFE HC Enable Analog 0x0000 GPIO 0x00 Forces DATA to be 0x0000 0x0000 GDIR 0xD0 GPIO 7 6 4 in 5 3 2 1 0 output 0x0000 GIE 0x00 0x0000 GIP 0x00 0x0000 BGTRIM 0x00 0x0000 TEST 0x00 0x0000 CTRL08 AFE_CTRL08 Timing NCO set up 0x0000 CTRL09 AFE_CTRL09 0x0000 CTRL10 AFE_CTRL10 0x0000 CTRL11 AFE_CTRL11 0x0000 CTRL12H AFE_...

Page 16: ...73M1903 MODEM ANALOG FRONT END DEMO BOARD User s Manual Revision 1 2 16 of 32 Copyright 2005 TERIDIAN Semiconductor Corporation This page was intentionally left blank ...

Page 17: ...cating with a host processor or DSP board The pins of this interface connector are configurable by 0 Ohm resistors R26 through R47 are option setting resistors Tables 3 2 and 3 3 describe the details of the jumper settings and 0 Ohm resistor population options J5 is a modular connector for phone line connection and J4 is for power connection from the main board or an external power supply J5 JS1 J...

Page 18: ... output is directed to a host controller through either JS1 or JP25 J2 Off hook control Three pin header that allows selection of the Off hook control by 73M1903 GPIO5 or by a Host CPU GPIO through JS1 or JP25 1 2 Off hook is controlled by 73M1903 GPIO5 73M1903 GPIO5 must be configured as an output 2 3 Off hook is controlled by a host output through either JS1 or JP25 JP1 FS Mode 2 pin header to s...

Page 19: ...nector pin 7 to be used as FS R37 FS JS1 connector pin 18 to be used as FS R38 RESET JS1 connector pin 4 to be used as RESET R39 AFEIN JS1 connector pin 4 to be used as AFEIN R40 SCLK JS1 connector pin 17 to be used as SCLK R41 SCLK JS1 connector pin 6 to be used as SCLK R42 SCLK JS1 connector pin 7 to be used as RESET R43 VCCD JS1 connector pin 2 to be used as VCCD 3 3V Digital supply R44 GNDD JS...

Page 20: ...n 4 00 2 00 0 69 0 62 1 17 1 18 0 27 0 35 0 33 0 20 0 15 Figure 3 2 PCB Dimensions PCB Dimensions Size 4 00x2 00 Height w components and solder 0 61 Environmental Operating Temperature 40 to 75 C function of crystal oscillator affected outside 10 C to 60 C Storage Temperature 65 to 150 C Power Supply DC Input Voltage powered from DC supply 3 3VDC 0 5V Supply Current 25mA off hook typical ...

Page 21: ...ls 73M1903 PC board layout 73M1903 Pin out 4 1 EXAMPLE OF TYPICAL SAMPLE RATE SETTINGS Following Table shows the examples of register values to setup for each specific sample rates using a 24 576MHz crystal All values are in Hex Sample Rate Registers Addr 7 2k Hz 8k Hz 9 6k Hz 14 4k Hz 16k Hz CTRL08 Addr 08 00 00 00 00 00 CTRL09 Addr 09 0A 0C 0A 0A 0A CTRL10 Addr 0A 10 11 22 26 17 CTRL11 Addr 0B 0...

Page 22: ...HEADER3 R13 232 R15 232 R17 38K R20 62K R22 38K R23 62K C3 0 15uF C5 0 15uF VCCA 1 2 3 4 5 6 7 8 9 10 JP2 HEADER 5X2 HOOK AFEOUT SCLK C6 3 3uF C7 10uF FS C11 0 1uF C12 0 1uF C13 0 1uF 4 1 3 2 U5 HD04 VCCD VCCD VCCA VCCD RINGD RINGD O 1 I 3 S 2 J4 power connector 1 TP1 GND 1 TP2 VCCA 1 TP3 TIP 1 TP4 RING RESET GND 1 TP6 RXAN 1 TP7 TXAN R26 0 1 TP8 TRAN1 R27 0 1 TP9 TRAN2 R30 0 1 TP10 RXAP 1 TP11 TX...

Page 23: ...2 U5 HD04 VCCD VCCD VCCA VCCD RINGD RINGD O 1 I 3 S 2 J4 power connector 1 3 2 4 Q4 FZT605CT 1 TP1 GND 1 TP2 VCCA 1 TP3 TIP 1 TP5 Q4C 1 TP4 RING RESET GND 1 TP6 RXAN 1 TP7 TXAN R26 0 1 TP8 TRAN1 R27 0 1 TP9 TRAN2 1 TP10 RXAP R30 0 1 TP11 TXAP R31 0 SCLK R32 0 FS RESET R33 0 AFEIN AFEOUT R34 0 R35 0 R36 0 R37 0 R38 0 R39 0 R40 0 R41 0 Various combinations of R26 R27 R30 47 can be used to select dif...

Page 24: ... 1 D6 22V nc 1 v 8 g 4 out 5 OSC1 NC VCCD 3A 2A 4A 1A 1B 2B 3B 4B T1 MIT4033L Sumida R24 22K 2 1 D2 CMR1F 04M F1 TR250 145 RAYCHEM POLYSWITCH CID coupling R14 62K R3 33K R4 13K R5 13K RING LREV detection R6 27K R7 1K R19 20K R11 9 1K R8 51K VCCD R9 9 1K ISOLATION BARRIER RING LIUB PPUB LREVB LIUCHK HOOK RING LREV detection R47 0 PPU Circuit R46 0 R16 100 C15 10uF This version supports Caller ID PP...

Page 25: ...7 C19 0 47uF 9 1 C20 22pF 10 1 D1 BZT52C16S 11 2 D5 D6 BZT52C22S 12 1 D8 S1A 13 1 E1 TB3100H 14 1 F1 MF R015 600 15 2 JP1 JP3 2 pin Header 16 1 JP2 HEADER 5X2 17 2 J1 J2 HEADER3 18 1 J4 power connector 19 1 J5 RJ 11 20 4 L1 L2 L3 L4 NLV32T 4R7 21 1 R2 2K 22 1 R8 51K 23 2 R9 R11 9 1K 24 2 R13 R15 232 25 1 R16 100 26 2 R17 R22 38K 27 2 R20 R23 62K 28 1 R24 22K 29 11 R27 R33 R37 R40 R42 R44 R45 R46 R...

Page 26: ... BZT52C22S 13 1 D8 S1A 14 1 E1 TB3100H 15 1 F1 MF R015 600 16 2 JP1 JP3 2 pin header 17 1 JP2 HEADER 5X2 18 1 JS1 CONN SOCKET 10x2 19 2 J1 J2 HEADER3 20 1 J4 power connector 21 1 J5 RJ 11 22 4 L1 L2 L3 L4 NLV32T 4R7 23 1 Q4 FZT605CT 24 1 Q6 MMST2222A 7 25 1 R2 2K 26 1 R3 33K 27 1 R8 51K 28 2 R9 R11 9 1K 29 2 R13 R15 232 30 3 R14 R20 R23 62K 31 1 R16 100 32 2 R17 R22 38K 33 1 R24 22K 34 1 R25 18 35...

Page 27: ...B3100H 18 1 F1 MF R015 600 19 2 JP1 JP3 2 pin header 20 1 JP2 HEADER 5X2 21 1 JS1 CONN SOCKET 10x2 22 2 J1 J2 HEADER3 23 1 J4 power connector 24 1 J5 RJ 11 25 4 L1 L2 L3 L4 NLV32T 4R7 26 2 Q1 Q5 BC857BW 27 2 Q2 Q3 CMPT6429 28 1 Q4 FZT605CT 29 2 R1 R29 75K 30 3 R2 R12 R19 20K 31 1 R3 33K 32 2 R4 R5 13K 33 1 R6 27K 34 1 R7 1K 35 1 R8 51K 36 2 R9 R11 9 1K 37 4 R10 R14 R20 R23 62K 38 2 R13 R15 51 39 3...

Page 28: ...ser s Manual Revision 1 2 28 of 32 Copyright 2005 TERIDIAN Semiconductor Corporation 4 4 DEMO BOARD PCB LAYOUT Figure 4 4 TERIDIAN 73M1903 DEMO BOARD Silk Screen Top Figure 4 5 TERIDIAN 73M1903 DEMO BOARD Top Signal Layer ...

Page 29: ... DEMO BOARD User s Manual Revision 1 2 29 of 32 Copyright 2005 TERIDIAN Semiconductor Corporation Figure 4 6 TERIDIAN 73M1903 DEMO BOARD Bottom Signal Layer Figure 4 7 TERIDIAN 73M1903 DEMO BOARD Supply Plane ...

Page 30: ...73M1903 DEMO BOARD User s Manual Revision 1 2 30 of 32 Copyright 2005 TERIDIAN Semiconductor Corporation Figure 4 8 TERIDIAN 73M1903 DEMO BOARD Ground Plane ...

Page 31: ...e OSCIN OSCOUT O 18 Crystal oscillator circuit output pin GPIO 0 7 I O 3 4 5 6 23 24 30 31 Software definable digital input output pins VREF O 13 Reference voltage pin Reflects internal Vref voltage RXAP I 15 Receive analog positive input RXAN I 14 Receive analog negative input TXAP O 12 Transmit analog positive output TXAN O 11 Transmit analog negative output SCLK O 8 Serial interface clock With ...

Page 32: ...SC and is made available for informational purposes only TERIDIAN assumes no obligation regarding future manufacture unless agreed to in writing If and when manufactured and sold this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TERIDIAN Semiconductor C...

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