73M1903 DEMO BOARD User’s Manual
Revision 1.2
31 of 32
© Copyright 2005 TERIDIAN Semiconductor Corporation
4.5 73M1903 PIN DESCRIPTION
Table 4-4: 73M1903 Pin Description
PIN NAME
TYPE PIN #
DESCRIPTION
VND
GND
1,22
Negative Digital Ground
VNA
GND
16
Negative Analog Ground
VPD
PWR
2,25
Positive Digital Supply
VPA
PWR
10
Positive Analog Supply
VPPLL
PWR
20
Positive PLL Supply, shared with VPD
VNPLL
PWR
17
Negative PLL Ground
RST
I 9
Master reset. When this pin is a logic 0 all registers are reset to
their default states; Weak-pulled high- default
OSCIN I
19
Crystal oscillator input. When providing an external clock
source, drive OSCIN.
OSCOUT
O
18
Crystal oscillator circuit output pin.
GPIO(0-7) I/O
3, 4, 5, 6,
23, 24,30,31
Software definable digital input/output pins.
VREF
O
13
Reference voltage pin (Reflects internal Vref voltage)
RXAP
I
15
Receive analog positive input.
RXAN
I
14
Receive analog negative input.
TXAP
O
12
Transmit analog positive output
TXAN
O
11
Transmit analog negative output
SCLK O
8
Serial interface clock. With SCLK continuous selected,
Frequency = 256*Fs ( =2.4576MHz for Fs=9.6kHz)
SDOUT
O
32
Serial data output (input to the host).
SDIN
I
29
Serial data input (output from the host)
FS
O
7
Frame synchronization. (frame starts on negative edge)
TYPE I
27
Type of frame sync. Open, weak-pulled high = early (mode1);
tied low = late (mode0)
SckMode I 28
Controls the SCLK behavior after FS. Open, weak-pulled high
= SCLK Continuous; tied low = 32 clocks per R/W cycle.
